From: Andrew Waterman <waterman@cs.berkeley.edu>
Date: Wed, 7 Sep 2016 06:58:57 +0000 (-0700)
Subject: Add rv32uf tests
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d2aeeedd0727804bf3a7d07b5efb4d00b67f0f33;p=riscv-tests.git

Add rv32uf tests
---

diff --git a/isa/Makefile b/isa/Makefile
index a13acd8..b8de54d 100644
--- a/isa/Makefile
+++ b/isa/Makefile
@@ -18,6 +18,7 @@ include $(src_dir)/rv32ui/Makefrag
 include $(src_dir)/rv32uc/Makefrag
 include $(src_dir)/rv32um/Makefrag
 include $(src_dir)/rv32ua/Makefrag
+include $(src_dir)/rv32uf/Makefrag
 include $(src_dir)/rv32si/Makefrag
 include $(src_dir)/rv32mi/Makefrag
 
@@ -71,6 +72,7 @@ $(eval $(call compile_template,rv32ui,-m32))
 $(eval $(call compile_template,rv32uc,-m32))
 $(eval $(call compile_template,rv32um,-m32))
 $(eval $(call compile_template,rv32ua,-m32))
+$(eval $(call compile_template,rv32uf,-m32))
 $(eval $(call compile_template,rv32si,-m32))
 $(eval $(call compile_template,rv32mi,-m32))
 ifeq ($(XLEN),64)
diff --git a/isa/rv32uf/Makefrag b/isa/rv32uf/Makefrag
new file mode 100644
index 0000000..bc958a7
--- /dev/null
+++ b/isa/rv32uf/Makefrag
@@ -0,0 +1,12 @@
+#=======================================================================
+# Makefrag for rv32uf tests
+#-----------------------------------------------------------------------
+
+rv32uf_sc_tests = \
+	fadd fdiv fclass fcmp fcvt fcvt_w fmadd fmin fsgnj \
+	ldst move recoding \
+
+rv32uf_p_tests = $(addprefix rv32uf-p-, $(rv32uf_sc_tests))
+rv32uf_v_tests = $(addprefix rv32uf-v-, $(rv32uf_sc_tests))
+
+spike32_tests += $(rv32uf_p_tests) $(rv32uf_v_tests)
diff --git a/isa/rv32uf/fadd.S b/isa/rv32uf/fadd.S
new file mode 100644
index 0000000..b832c3d
--- /dev/null
+++ b/isa/rv32uf/fadd.S
@@ -0,0 +1,7 @@
+# See LICENSE for license details.
+
+#include "riscv_test.h"
+#undef RVTEST_RV64UF
+#define RVTEST_RV64UF RVTEST_RV32UF
+
+#include "../rv64uf/fadd.S"
diff --git a/isa/rv32uf/fclass.S b/isa/rv32uf/fclass.S
new file mode 100644
index 0000000..19bbcc5
--- /dev/null
+++ b/isa/rv32uf/fclass.S
@@ -0,0 +1,7 @@
+# See LICENSE for license details.
+
+#include "riscv_test.h"
+#undef RVTEST_RV64UF
+#define RVTEST_RV64UF RVTEST_RV32UF
+
+#include "../rv64uf/fclass.S"
diff --git a/isa/rv32uf/fcmp.S b/isa/rv32uf/fcmp.S
new file mode 100644
index 0000000..2dbf451
--- /dev/null
+++ b/isa/rv32uf/fcmp.S
@@ -0,0 +1,7 @@
+# See LICENSE for license details.
+
+#include "riscv_test.h"
+#undef RVTEST_RV64UF
+#define RVTEST_RV64UF RVTEST_RV32UF
+
+#include "../rv64uf/fcmp.S"
diff --git a/isa/rv32uf/fcvt.S b/isa/rv32uf/fcvt.S
new file mode 100644
index 0000000..627f1f2
--- /dev/null
+++ b/isa/rv32uf/fcvt.S
@@ -0,0 +1,7 @@
+# See LICENSE for license details.
+
+#include "riscv_test.h"
+#undef RVTEST_RV64UF
+#define RVTEST_RV64UF RVTEST_RV32UF
+
+#include "../rv64uf/fcvt.S"
diff --git a/isa/rv32uf/fcvt_w.S b/isa/rv32uf/fcvt_w.S
new file mode 100644
index 0000000..3447530
--- /dev/null
+++ b/isa/rv32uf/fcvt_w.S
@@ -0,0 +1,7 @@
+# See LICENSE for license details.
+
+#include "riscv_test.h"
+#undef RVTEST_RV64UF
+#define RVTEST_RV64UF RVTEST_RV32UF
+
+#include "../rv64uf/fcvt_w.S"
diff --git a/isa/rv32uf/fdiv.S b/isa/rv32uf/fdiv.S
new file mode 100644
index 0000000..12aaa3d
--- /dev/null
+++ b/isa/rv32uf/fdiv.S
@@ -0,0 +1,7 @@
+# See LICENSE for license details.
+
+#include "riscv_test.h"
+#undef RVTEST_RV64UF
+#define RVTEST_RV64UF RVTEST_RV32UF
+
+#include "../rv64uf/fdiv.S"
diff --git a/isa/rv32uf/fmadd.S b/isa/rv32uf/fmadd.S
new file mode 100644
index 0000000..8a5aacb
--- /dev/null
+++ b/isa/rv32uf/fmadd.S
@@ -0,0 +1,7 @@
+# See LICENSE for license details.
+
+#include "riscv_test.h"
+#undef RVTEST_RV64UF
+#define RVTEST_RV64UF RVTEST_RV32UF
+
+#include "../rv64uf/fmadd.S"
diff --git a/isa/rv32uf/fmin.S b/isa/rv32uf/fmin.S
new file mode 100644
index 0000000..9231d01
--- /dev/null
+++ b/isa/rv32uf/fmin.S
@@ -0,0 +1,7 @@
+# See LICENSE for license details.
+
+#include "riscv_test.h"
+#undef RVTEST_RV64UF
+#define RVTEST_RV64UF RVTEST_RV32UF
+
+#include "../rv64uf/fmin.S"
diff --git a/isa/rv32uf/fsgnj.S b/isa/rv32uf/fsgnj.S
new file mode 100644
index 0000000..6d05a23
--- /dev/null
+++ b/isa/rv32uf/fsgnj.S
@@ -0,0 +1,7 @@
+# See LICENSE for license details.
+
+#include "riscv_test.h"
+#undef RVTEST_RV64UF
+#define RVTEST_RV64UF RVTEST_RV32UF
+
+#include "../rv64uf/fsgnj.S"
diff --git a/isa/rv32uf/ldst.S b/isa/rv32uf/ldst.S
new file mode 100644
index 0000000..01f7fef
--- /dev/null
+++ b/isa/rv32uf/ldst.S
@@ -0,0 +1,38 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# ldst.S
+#-----------------------------------------------------------------------------
+#
+# This test verifies that flw, fld, fsw, and fsd work properly.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32UF
+RVTEST_CODE_BEGIN
+
+  TEST_CASE(2, a0, 0x40000000, la a1, tdat; flw f1, 4(a1); fsw f1, 20(a1); lw a0, 20(a1))
+  TEST_CASE(3, a0, 0xbf800000, la a1, tdat; flw f1, 0(a1); fsw f1, 24(a1); lw a0, 24(a1))
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+tdat:
+.word 0xbf800000
+.word 0x40000000
+.word 0x40400000
+.word 0xc0800000
+.word 0xdeadbeef
+.word 0xcafebabe
+.word 0xabad1dea
+.word 0x1337d00d
+
+RVTEST_DATA_END
diff --git a/isa/rv32uf/move.S b/isa/rv32uf/move.S
new file mode 100644
index 0000000..949da6f
--- /dev/null
+++ b/isa/rv32uf/move.S
@@ -0,0 +1,7 @@
+# See LICENSE for license details.
+
+#include "riscv_test.h"
+#undef RVTEST_RV64UF
+#define RVTEST_RV64UF RVTEST_RV32UF
+
+#include "../rv64uf/move.S"
diff --git a/isa/rv32uf/recoding.S b/isa/rv32uf/recoding.S
new file mode 100644
index 0000000..5dc0113
--- /dev/null
+++ b/isa/rv32uf/recoding.S
@@ -0,0 +1,7 @@
+# See LICENSE for license details.
+
+#include "riscv_test.h"
+#undef RVTEST_RV64UF
+#define RVTEST_RV64UF RVTEST_RV32UF
+
+#include "../rv64uf/recoding.S"
diff --git a/isa/rv64uf/fcvt.S b/isa/rv64uf/fcvt.S
index 7bcb49a..a9a1b59 100644
--- a/isa/rv64uf/fcvt.S
+++ b/isa/rv64uf/fcvt.S
@@ -23,11 +23,13 @@ RVTEST_CODE_BEGIN
   TEST_INT_FP_OP_S( 4, fcvt.s.wu,                   2.0,  2);
   TEST_INT_FP_OP_S( 5, fcvt.s.wu,           4.2949673e9, -2);
 
+#ifndef __riscv32
   TEST_INT_FP_OP_S( 6,  fcvt.s.l,                   2.0,  2);
   TEST_INT_FP_OP_S( 7,  fcvt.s.l,                  -2.0, -2);
 
   TEST_INT_FP_OP_S( 8, fcvt.s.lu,                   2.0,  2);
   TEST_INT_FP_OP_S( 9, fcvt.s.lu,          1.8446744e19, -2);
+#endif
 
   TEST_PASSFAIL
 
diff --git a/isa/rv64uf/fcvt_w.S b/isa/rv64uf/fcvt_w.S
index 92faffa..bf7878a 100644
--- a/isa/rv64uf/fcvt_w.S
+++ b/isa/rv64uf/fcvt_w.S
@@ -35,6 +35,7 @@ RVTEST_CODE_BEGIN
   TEST_FP_INT_OP_S(18, fcvt.wu.s, 0x10,          0, -3e9, rtz);
   TEST_FP_INT_OP_S(19, fcvt.wu.s, 0x00, 3000000000,  3e9, rtz);
 
+#ifndef __riscv32
   TEST_FP_INT_OP_S(22,  fcvt.l.s, 0x01,         -1, -1.1, rtz);
   TEST_FP_INT_OP_S(23,  fcvt.l.s, 0x00,         -1, -1.0, rtz);
   TEST_FP_INT_OP_S(24,  fcvt.l.s, 0x01,          0, -0.9, rtz);
@@ -49,29 +50,36 @@ RVTEST_CODE_BEGIN
   TEST_FP_INT_OP_S(36, fcvt.lu.s, 0x00,          1,  1.0, rtz);
   TEST_FP_INT_OP_S(37, fcvt.lu.s, 0x01,          1,  1.1, rtz);
   TEST_FP_INT_OP_S(38, fcvt.lu.s, 0x10,          0, -3e9, rtz);
+#endif
 
   # test negative NaN, negative infinity conversion
   TEST_CASE( 42, x1, 0x000000007fffffff, la x1, tdat  ; flw f1,  0(x1); fcvt.w.s x1, f1)
-  TEST_CASE( 43, x1, 0x7fffffffffffffff, la x1, tdat  ; flw f1,  0(x1); fcvt.l.s x1, f1)
   TEST_CASE( 44, x1, 0xffffffff80000000, la x1, tdat  ; flw f1,  8(x1); fcvt.w.s x1, f1)
+#ifndef __riscv32
+  TEST_CASE( 43, x1, 0x7fffffffffffffff, la x1, tdat  ; flw f1,  0(x1); fcvt.l.s x1, f1)
   TEST_CASE( 45, x1, 0x8000000000000000, la x1, tdat  ; flw f1,  8(x1); fcvt.l.s x1, f1)
+#endif
 
   # test positive NaN, positive infinity conversion
   TEST_CASE( 52, x1, 0x000000007fffffff, la x1, tdat  ; flw f1,  4(x1); fcvt.w.s x1, f1)
-  TEST_CASE( 53, x1, 0x7fffffffffffffff, la x1, tdat  ; flw f1,  4(x1); fcvt.l.s x1, f1)
   TEST_CASE( 54, x1, 0x000000007fffffff, la x1, tdat  ; flw f1, 12(x1); fcvt.w.s x1, f1)
+#ifndef __riscv32
+  TEST_CASE( 53, x1, 0x7fffffffffffffff, la x1, tdat  ; flw f1,  4(x1); fcvt.l.s x1, f1)
   TEST_CASE( 55, x1, 0x7fffffffffffffff, la x1, tdat  ; flw f1, 12(x1); fcvt.l.s x1, f1)
+#endif
 
   # test NaN, infinity conversions to unsigned integer
   TEST_CASE( 62, x1, 0xffffffffffffffff, la x1, tdat  ; flw f1,  0(x1); fcvt.wu.s x1, f1)
   TEST_CASE( 63, x1, 0xffffffffffffffff, la x1, tdat  ; flw f1,  4(x1); fcvt.wu.s x1, f1)
   TEST_CASE( 64, x1,                  0, la x1, tdat  ; flw f1,  8(x1); fcvt.wu.s x1, f1)
   TEST_CASE( 65, x1, 0xffffffffffffffff, la x1, tdat  ; flw f1, 12(x1); fcvt.wu.s x1, f1)
+#ifndef __riscv32
   TEST_CASE( 66, x1, 0xffffffffffffffff, la x1, tdat  ; flw f1,  0(x1); fcvt.lu.s x1, f1)
   TEST_CASE( 67, x1, 0xffffffffffffffff, la x1, tdat  ; flw f1,  4(x1); fcvt.lu.s x1, f1)
   TEST_CASE( 68, x1,                  0, la x1, tdat  ; flw f1,  8(x1); fcvt.lu.s x1, f1)
   TEST_CASE( 69, x1, 0xffffffffffffffff, la x1, tdat  ; flw f1, 12(x1); fcvt.lu.s x1, f1)
-   
+#endif
+
   TEST_PASSFAIL
 
 RVTEST_CODE_END