From: lkcl <lkcl@web>
Date: Sun, 23 Oct 2022 11:23:17 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~48
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d2d1982e8fb6151c788ac14691e87a0707842d11;p=libreriscv.git

---

diff --git a/openpower/sv/bitmanip.mdwn b/openpower/sv/bitmanip.mdwn
index f16955f85..6b75c68d0 100644
--- a/openpower/sv/bitmanip.mdwn
+++ b/openpower/sv/bitmanip.mdwn
@@ -243,6 +243,12 @@ Power ISA is missing LD/ST with shift, which is present in both ARM and x86.
 Too complex to add more LD/ST, a compromise is to add shift-and-add.
 Replaces a pair of explicit instructions in hot-loops.
 
+```
+# 1.6.27 Z23-FORM
+    |0     |6     |11    |15 |16     |21 |23    |31 |
+    | PO   |  RT  |   RA     |   RB  |sm |   XO |Rc |
+```
+
 ```
 uint_xlen_t shadd(uint_xlen_t rs1, uint_xlen_t rs2, uint8_t sh) {
     sh = sh & 0x3;