From: Jakub Jelinek Date: Thu, 27 Jun 2019 11:13:10 +0000 (+0200) Subject: re PR target/90991 (_mm_loadu_ps instrinsic translates to vmovaps in combination... X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d2d604d83edb86ce3f492d03900fb29dea97725d;p=gcc.git re PR target/90991 (_mm_loadu_ps instrinsic translates to vmovaps in combination with _mm512_insertf32x4) PR target/90991 * config/i386/sse.md (avx_vec_concat): Use nonimmediate_operand instead of register_operand for operands[1], add m to its constraints if operands[2] uses "C" constraint. Ensure in condition that if operands[2] is not 0, then operands[1] is not a MEM. For last two alternatives, use unaligned loads instead of aligned if operands[1] is misaligned_operand. * gcc.target/i386/avx2-pr90991-1.c: New test. * gcc.target/i386/avx512dq-pr90991-2.c: New test. From-SVN: r272745 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index a366de95455..73c0be048ac 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,13 @@ +2019-06-27 Jakub Jelinek + + PR target/90991 + * config/i386/sse.md (avx_vec_concat): Use nonimmediate_operand + instead of register_operand for operands[1], add m to its constraints + if operands[2] uses "C" constraint. Ensure in condition that if + operands[2] is not 0, then operands[1] is not a MEM. For last two + alternatives, use unaligned loads instead of aligned if operands[1] is + misaligned_operand. + 2019-06-27 Martin Liska * asan.c (asan_emit_allocas_unpoison): Remove obviously diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index 29f16bc558f..8b4f6c185d0 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -20743,9 +20743,11 @@ (define_insn "avx_vec_concat" [(set (match_operand:V_256_512 0 "register_operand" "=x,v,x,Yv") (vec_concat:V_256_512 - (match_operand: 1 "register_operand" "x,v,x,v") + (match_operand: 1 "nonimmediate_operand" "x,v,xm,vm") (match_operand: 2 "nonimm_or_0_operand" "xm,vm,C,C")))] - "TARGET_AVX" + "TARGET_AVX + && (operands[2] == CONST0_RTX (mode) + || !MEM_P (operands[1]))" { switch (which_alternative) { @@ -20771,27 +20773,63 @@ switch (get_attr_mode (insn)) { case MODE_V16SF: - return "vmovaps\t{%1, %t0|%t0, %1}"; + if (misaligned_operand (operands[1], mode)) + return "vmovups\t{%1, %t0|%t0, %1}"; + else + return "vmovaps\t{%1, %t0|%t0, %1}"; case MODE_V8DF: - return "vmovapd\t{%1, %t0|%t0, %1}"; + if (misaligned_operand (operands[1], mode)) + return "vmovupd\t{%1, %t0|%t0, %1}"; + else + return "vmovapd\t{%1, %t0|%t0, %1}"; case MODE_V8SF: - return "vmovaps\t{%1, %x0|%x0, %1}"; + if (misaligned_operand (operands[1], mode)) + return "vmovups\t{%1, %x0|%x0, %1}"; + else + return "vmovaps\t{%1, %x0|%x0, %1}"; case MODE_V4DF: - return "vmovapd\t{%1, %x0|%x0, %1}"; + if (misaligned_operand (operands[1], mode)) + return "vmovupd\t{%1, %x0|%x0, %1}"; + else + return "vmovapd\t{%1, %x0|%x0, %1}"; case MODE_XI: - if (which_alternative == 2) - return "vmovdqa\t{%1, %t0|%t0, %1}"; - else if (GET_MODE_SIZE (mode) == 8) - return "vmovdqa64\t{%1, %t0|%t0, %1}"; + if (misaligned_operand (operands[1], mode)) + { + if (which_alternative == 2) + return "vmovdqu\t{%1, %t0|%t0, %1}"; + else if (GET_MODE_SIZE (mode) == 8) + return "vmovdqu64\t{%1, %t0|%t0, %1}"; + else + return "vmovdqu32\t{%1, %t0|%t0, %1}"; + } else - return "vmovdqa32\t{%1, %t0|%t0, %1}"; + { + if (which_alternative == 2) + return "vmovdqa\t{%1, %t0|%t0, %1}"; + else if (GET_MODE_SIZE (mode) == 8) + return "vmovdqa64\t{%1, %t0|%t0, %1}"; + else + return "vmovdqa32\t{%1, %t0|%t0, %1}"; + } case MODE_OI: - if (which_alternative == 2) - return "vmovdqa\t{%1, %x0|%x0, %1}"; - else if (GET_MODE_SIZE (mode) == 8) - return "vmovdqa64\t{%1, %x0|%x0, %1}"; + if (misaligned_operand (operands[1], mode)) + { + if (which_alternative == 2) + return "vmovdqu\t{%1, %x0|%x0, %1}"; + else if (GET_MODE_SIZE (mode) == 8) + return "vmovdqu64\t{%1, %x0|%x0, %1}"; + else + return "vmovdqu32\t{%1, %x0|%x0, %1}"; + } else - return "vmovdqa32\t{%1, %x0|%x0, %1}"; + { + if (which_alternative == 2) + return "vmovdqa\t{%1, %x0|%x0, %1}"; + else if (GET_MODE_SIZE (mode) == 8) + return "vmovdqa64\t{%1, %x0|%x0, %1}"; + else + return "vmovdqa32\t{%1, %x0|%x0, %1}"; + } default: gcc_unreachable (); } diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 732194f37ca..41918c86677 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,9 @@ +2019-06-27 Jakub Jelinek + + PR target/90991 + * gcc.target/i386/avx2-pr90991-1.c: New test. + * gcc.target/i386/avx512dq-pr90991-2.c: New test. + 2019-06-27 Jan Beulich * gcc.target/i386/gfni-4.c: Pass -msse2. diff --git a/gcc/testsuite/gcc.target/i386/avx2-pr90991-1.c b/gcc/testsuite/gcc.target/i386/avx2-pr90991-1.c new file mode 100644 index 00000000000..1f0467efcb1 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-pr90991-1.c @@ -0,0 +1,50 @@ +/* PR target/90991 */ +/* { dg-do compile } */ +/* { dg-options "-O2 -mavx2 -masm=att" } */ +/* { dg-final { scan-assembler-times "vmovaps\[ \t]\+\\(\[^\n\r]*\\), %xmm0" 1 } } */ +/* { dg-final { scan-assembler-times "vmovapd\[ \t]\+\\(\[^\n\r]*\\), %xmm0" 1 } } */ +/* { dg-final { scan-assembler-times "vmovdqa\[ \t]\+\\(\[^\n\r]*\\), %xmm0" 1 } } */ +/* { dg-final { scan-assembler-times "vmovups\[ \t]\+\\(\[^\n\r]*\\), %xmm0" 1 } } */ +/* { dg-final { scan-assembler-times "vmovupd\[ \t]\+\\(\[^\n\r]*\\), %xmm0" 1 } } */ +/* { dg-final { scan-assembler-times "vmovdqu\[ \t]\+\\(\[^\n\r]*\\), %xmm0" 1 } } */ +/* { dg-final { scan-assembler-not "vmovaps\[^\n\r]*xmm0\[^\n\r]*xmm0" } } */ +/* { dg-final { scan-assembler-not "vmovapd\[^\n\r]*xmm0\[^\n\r]*xmm0" } } */ +/* { dg-final { scan-assembler-not "vmovdqa\[^\n\r]*xmm0\[^\n\r]*xmm0" } } */ + +#include + +__m256 +f1 (void *a) +{ + return _mm256_insertf128_ps (_mm256_set1_ps (0.0f), _mm_load_ps (a), 0); +} + +__m256d +f2 (void *a) +{ + return _mm256_insertf128_pd (_mm256_set1_pd (0.0), _mm_load_pd (a), 0); +} + +__m256i +f3 (void *a) +{ + return _mm256_insertf128_si256 (_mm256_set1_epi32 (0), _mm_load_si128 (a), 0); +} + +__m256 +f4 (void *a) +{ + return _mm256_insertf128_ps (_mm256_set1_ps (0.0f), _mm_loadu_ps (a), 0); +} + +__m256d +f5 (void *a) +{ + return _mm256_insertf128_pd (_mm256_set1_pd (0.0), _mm_loadu_pd (a), 0); +} + +__m256i +f6 (void *a) +{ + return _mm256_insertf128_si256 (_mm256_set1_epi32 (0), _mm_loadu_si128 (a), 0); +} diff --git a/gcc/testsuite/gcc.target/i386/avx512dq-pr90991-2.c b/gcc/testsuite/gcc.target/i386/avx512dq-pr90991-2.c new file mode 100644 index 00000000000..7699c3149ae --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512dq-pr90991-2.c @@ -0,0 +1,47 @@ +/* PR target/90991 */ +/* { dg-do compile } */ +/* { dg-options "-O2 -mavx512dq -masm=att -mtune=intel" } */ +/* { dg-final { scan-assembler-times "vmovaps\[ \t]\+\\(\[^\n\r]*\\), %ymm0" 1 } } */ +/* { dg-final { scan-assembler-times "vmovapd\[ \t]\+\\(\[^\n\r]*\\), %ymm0" 1 } } */ +/* { dg-final { scan-assembler-times "vmovdqa\[ \t]\+\\(\[^\n\r]*\\), %ymm0" 1 } } */ +/* { dg-final { scan-assembler-times "vmovups\[ \t]\+\\(\[^\n\r]*\\), %ymm0" 1 } } */ +/* { dg-final { scan-assembler-times "vmovupd\[ \t]\+\\(\[^\n\r]*\\), %ymm0" 1 } } */ +/* { dg-final { scan-assembler-times "vmovdqu\[ \t]\+\\(\[^\n\r]*\\), %ymm0" 1 } } */ + +#include + +__m512 +f1 (void *a) +{ + return _mm512_insertf32x8 (_mm512_set1_ps (0.0f), _mm256_load_ps (a), 0); +} + +__m512d +f2 (void *a) +{ + return _mm512_insertf64x4 (_mm512_set1_pd (0.0), _mm256_load_pd (a), 0); +} + +__m512i +f3 (void *a) +{ + return _mm512_inserti32x8 (_mm512_set1_epi32 (0), _mm256_load_si256 (a), 0); +} + +__m512 +f4 (void *a) +{ + return _mm512_insertf32x8 (_mm512_set1_ps (0.0f), _mm256_loadu_ps (a), 0); +} + +__m512d +f5 (void *a) +{ + return _mm512_insertf64x4 (_mm512_set1_pd (0.0), _mm256_loadu_pd (a), 0); +} + +__m512i +f6 (void *a) +{ + return _mm512_inserti32x8 (_mm512_set1_epi32 (0), _mm256_loadu_si256 (a), 0); +}