From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 22 Apr 2020 20:59:56 +0000 (-0700)
Subject: xilinx: improve xilinx_dffopt message
X-Git-Tag: working-ls180~594^2~4
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d2d90e4504a0fb43c35584484e0b949be7225b2b;p=yosys.git

xilinx: improve xilinx_dffopt message
---

diff --git a/techlibs/xilinx/xilinx_dffopt.cc b/techlibs/xilinx/xilinx_dffopt.cc
index c608db883..c9d63c9f7 100644
--- a/techlibs/xilinx/xilinx_dffopt.cc
+++ b/techlibs/xilinx/xilinx_dffopt.cc
@@ -292,18 +292,21 @@ unmap:
 				LutData final_lut;
 				if (worthy_post_r) {
 					final_lut = lut_d_post_r;
-					log("  Merging R LUT for %s/%s (%d -> %d)\n", log_id(cell), log_id(sig_Q.wire), GetSize(lut_d.second), GetSize(final_lut.second));
 				} else if (worthy_post_s) {
 					final_lut = lut_d_post_s;
-					log("  Merging S LUT for %s/%s (%d -> %d)\n", log_id(cell), log_id(sig_Q.wire), GetSize(lut_d.second), GetSize(final_lut.second));
 				} else if (worthy_post_ce) {
 					final_lut = lut_d_post_ce;
-					log("  Merging CE LUT for %s/%s (%d -> %d)\n", log_id(cell), log_id(sig_Q.wire), GetSize(lut_d.second), GetSize(final_lut.second));
 				} else {
 					// Nothing to do here.
 					continue;
 				}
 
+				std::string ports;
+				if (worthy_post_r) ports += " + R";
+				if (worthy_post_s) ports += " + S";
+				if (worthy_post_ce) ports += " + CE";
+				log("  Merging D%s LUTs for %s/%s (%d -> %d)\n", ports.c_str(), log_id(cell), log_id(sig_Q.wire), GetSize(lut_d.second), GetSize(final_lut.second));
+
 				// Okay, we're doing it.  Unmap ports.
 				if (worthy_post_r) {
 					cell->unsetParam(ID(IS_R_INVERTED));