From: Michael Snyder Date: Wed, 23 Jul 2003 21:23:32 +0000 (+0000) Subject: 2003-06-27 Michael Snyder X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d2f18ae42afc58479c4cbfcc5e9a790b42858f60;p=binutils-gdb.git 2003-06-27 Michael Snyder * gencode.c (op tab): Implement movca.l. --- diff --git a/sim/sh/ChangeLog b/sim/sh/ChangeLog index ad4bd8fcfa0..2b6624d8973 100644 --- a/sim/sh/ChangeLog +++ b/sim/sh/ChangeLog @@ -4,6 +4,7 @@ 2003-06-27 Michael Snyder + * gencode.c (op tab): Implement movca.l. * gencode.c (op movsxy_tab): Fix an error in the bit pattern. * gencode.c (gensim_caselist): The movy instructions use registers R6 and R7 (not R4 and R5 like the movx insns). diff --git a/sim/sh/gencode.c b/sim/sh/gencode.c index e8e780fec9f..ea6d323eab0 100644 --- a/sim/sh/gencode.c +++ b/sim/sh/gencode.c @@ -750,9 +750,10 @@ op tab[] = "R0 = ((i + 4 + PH2T (PC)) & ~0x3);", }, - { "0", "", "movca.l @R0, ", "0000nnnn11000011", - "/* FIXME: Not implemented */", - "RAISE_EXCEPTION (SIGILL);", + { "", "n0", "movca.l R0, @", "0000nnnn11000011", + "/* We don't simulate cache, so this insn is identical to mov. */", + "MA (1);", + "WLAT (R[n], R[0]);", }, { "n", "", "movt ", "0000nnnn00101001",