From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Fri, 15 May 2020 13:15:41 +0000 (+0100)
Subject: link countzero in to Logical pipeline
X-Git-Tag: div_pipeline~1203
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d2f6b2060f73b81c0a2f6fbbd10ab2a6cf65d628;p=soc.git

link countzero in to Logical pipeline
---

diff --git a/src/soc/logical/main_stage.py b/src/soc/logical/main_stage.py
index 01405644..76be8a64 100644
--- a/src/soc/logical/main_stage.py
+++ b/src/soc/logical/main_stage.py
@@ -11,6 +11,11 @@ from soc.logical.pipe_data import ALUInputData
 from soc.alu.pipe_data import ALUOutputData
 from ieee754.part.partsig import PartitionedSignal
 from soc.decoder.power_enums import InternalOp
+from soc.countzero.countzero import ZeroCounter
+
+from soc.decoder.power_fields import DecodeFields
+from soc.decoder.power_fieldsn import SignalBitRange
+
 
 def array_of(count, bitwidth):
     res = []
@@ -22,6 +27,8 @@ def array_of(count, bitwidth):
 class LogicalMainStage(PipeModBase):
     def __init__(self, pspec):
         super().__init__(pspec, "main")
+        self.fields = DecodeFields(SignalBitRange, [self.i.ctx.op.insn])
+        self.fields.create_specs()
 
     def ispec(self):
         return ALUInputData(self.pspec)
@@ -101,7 +108,15 @@ class LogicalMainStage(PipeModBase):
                     comb += o[32].eq(par1)
 
             ###### cntlz #######
-            # TODO with m.Case(InternalOp.OP_CNTZ):
+            with m.Case(InternalOp.OP_CNTZ):
+                x_fields = self.fields.instrs['X']
+                XO = Signal(x_fields['XO'][0:-1].shape())
+                m.submodules.countz = countz = ZeroCounter()
+                comb += countz.rs_i.eq(a)
+                comb += countz.is_32bit_i.eq(op.is_32bit)
+                comb += countz.count_right_i.eq(XO[-1])
+                comb += o.eq(countz.result_o)
+
             ###### bpermd #######
             # TODO with m.Case(InternalOp.OP_BPERM): - not in microwatt