From: lkcl Date: Wed, 29 Mar 2023 22:45:07 +0000 (+0100) Subject: (no commit message) X-Git-Tag: opf_rfc_ls012_v1~220 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d2fdce53b05b6a0b7fd19545007070fbe61aafda;p=libreriscv.git --- diff --git a/openpower/sv/rfc/ls010.mdwn b/openpower/sv/rfc/ls010.mdwn index 0fd47f3c5..64dc7499c 100644 --- a/openpower/sv/rfc/ls010.mdwn +++ b/openpower/sv/rfc/ls010.mdwn @@ -275,7 +275,7 @@ new 64-bit encoding space, alongside EXT1xx. | 0-5 | 6 | 7 | 8-31 | 32| Description | |-----|---|---|-------|---|------------------------------------| -| PO | 0 | x | xxxx | 0 | EXT200-232 or `RESERVED2` (56-bit) | +| PO | 0 | x | xxxx | 0 | EXT200-231 or `RESERVED2` (56-bit) | | PO | 0 | 0 | !zero | 1 | SVP64Single:EXT232-263, or `RESERVED3` | | PO | 0 | 0 | 0000 | 1 | Scalar EXT232-263 | | PO | 0 | 1 | nnnn | 1 | SVP64:EXT232-263 | @@ -301,6 +301,21 @@ that may not be revoked under any circumstances. A useful way to think of this is that the Prefix Encoding is, like the 8086 REP instruction, an independent 32-bit Defined Word.* +Ecoding spaces and their potential are illustrated: + +| Encoding | Available bits | Scalar | Vectoriseable | SVP64Single | +|----------|----------------|--------|---------------|--------------| +|EXT000-063| 32 | yes | yes |yes | +|EXT100-163| 64 | yes | no |no | +|EXT200-231| 56 | N/A |not applicable |not applicable| +|EXT232-263| 32 | yes | yes |yes | +|EXT300-363| 32 | yes | no |no | + +Prefixed-Prefixed (96-bit) instructions are prohibited. EXT200-231 presently +remains unallocated (RESERVED) and therefore its potential is not yet defined +(Not Applicable). Additional Sandbox Opcodes are defined as EXT254 and EXT322, +alongside EXT022. + # Remapped Encoding (`RM[0:23]`) In the SVP64 Vector Prefix spaces, the 24 bits 8-31 are termed `RM`. Bits 32-37 are