From: Luke Kenneth Casson Leighton Date: Tue, 16 Nov 2021 13:36:26 +0000 (+0000) Subject: rename regports for bitvectors so that X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d2fe553b8e8365c22fdf239f00e3f6bda20e152c;p=soc.git rename regports for bitvectors so that * read regfile can SET the bitvector * write regfile can CLEAR the bitvector --- diff --git a/src/soc/regfile/regfiles.py b/src/soc/regfile/regfiles.py index 8461181a..244b2f67 100644 --- a/src/soc/regfile/regfiles.py +++ b/src/soc/regfile/regfiles.py @@ -290,7 +290,20 @@ class RegFiles: vec = RegFileArray(1, rf.depth) # get read/write port specs and create bitvector ports with same names wr_spec, rd_spec = rf.get_port_specs() - create_ports(vec, wr_spec, rd_spec) + # ok, this is complicated/fun. + # issue phase for checking whether to issue only needs one read port + # however during regfile-read, the corresponding bitvector needs to + # be *WRITTEN* to (a 1), and during regfile-write, the corresponding + # bitvector *ALSO* needs to be wrtten (a 0). therefore we need to + # MERGE the wr_spec and rd_spec with some appropriate name prefixes + # to make sure they do not clash + rd_bvspec = {'issue': 'issue'} + wr_bvspec = {} + for k, port in wr_spec.items(): + wr_bvspec["wr_%s" % k] = "wr_%s" % port + for k, port in rd_spec.items(): + wr_bvspec["rd_%s" % k] = "rd_%s" % port + create_ports(vec, wr_bvspec, rd_bvspec) return vec def elaborate_into(self, m, platform): diff --git a/src/soc/simple/core.py b/src/soc/simple/core.py index 45e30c61..1e9c6351 100644 --- a/src/soc/simple/core.py +++ b/src/soc/simple/core.py @@ -488,7 +488,7 @@ class NonProductionCore(ControlBase): wport = rfile.w_ports[rpidx] if self.make_hazard_vecs: wv = regs.wv[regfile.lower()] - wvport = wv.w_ports[rpidx] # write-vector (bit-level hazard ctrl) + wvport = wv.w_ports["wr_"+rpidx] # write-vec bit-level hazard ctrl fspecs = fspec if not isinstance(fspecs, list):