From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 25 Jun 2019 06:37:01 +0000 (-0700)
Subject: nullptr check
X-Git-Tag: working-ls180~1237^2~40
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d2fed0a7f1bb72ee285657b974f4996c77641a23;p=yosys.git

nullptr check
---

diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc
index cd7954427..52ca47a49 100644
--- a/passes/techmap/abc9.cc
+++ b/passes/techmap/abc9.cc
@@ -124,6 +124,7 @@ void handle_loops(RTLIL::Design *design)
 				RTLIL::SigSpec sig;
 				for (auto b : it->second) {
 					Wire *w = b.wire;
+					if (!w) continue;
 					if (w->port_output) {
 						log_assert(w->get_bool_attribute("\\abc_scc_break"));
 						w = module->wire(stringf("%s.abci", w->name.c_str()));