From: Giacomo Travaglini Date: Wed, 8 Apr 2020 08:35:07 +0000 (+0100) Subject: arch-arm: Remove unnecessary haveGICv3CPUInterface X-Git-Tag: v20.0.0.0~198 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d30068d5387dc4f7550606ea4d3eb2b6d55a02ce;p=gem5.git arch-arm: Remove unnecessary haveGICv3CPUInterface This is not needed since the ISA class could just check if the gicv3CpuInterface ptr is different than nullptr Change-Id: I6d562a5d9ff2568774b6958f03f04d878266ca8f Signed-off-by: Giacomo Travaglini Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27711 Reviewed-by: Ciro Santilli Tested-by: kokoro --- diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc index 2cc0f950c..a3e0ce6c2 100644 --- a/src/arch/arm/isa.cc +++ b/src/arch/arm/isa.cc @@ -60,7 +60,7 @@ namespace ArmISA ISA::ISA(Params *p) : BaseISA(p), system(NULL), _decoderFlavor(p->decoderFlavor), _vecRegRenameMode(Enums::Full), - pmu(p->pmu), haveGICv3CPUInterface(false), impdefAsNop(p->impdef_nop), + pmu(p->pmu), impdefAsNop(p->impdef_nop), afterStartup(false) { miscRegs[MISCREG_SCTLR_RST] = 0; @@ -428,7 +428,6 @@ ISA::startup(ThreadContext *tc) if (system) { Gicv3 *gicv3 = dynamic_cast(system->getGIC()); if (gicv3) { - haveGICv3CPUInterface = true; gicv3CpuInterface.reset(gicv3->getCPUInterface(tc->contextId())); gicv3CpuInterface->setISA(this); gicv3CpuInterface->setThreadContext(tc); @@ -744,7 +743,7 @@ ISA::readMiscReg(int misc_reg, ThreadContext *tc) (haveVirtualization ? 0x0000000000000200 : 0) | // EL2 (haveSecurity ? 0x0000000000002000 : 0) | // EL3 (haveSVE ? 0x0000000100000000 : 0) | // SVE - (haveGICv3CPUInterface ? 0x0000000001000000 : 0); + (gicv3CpuInterface ? 0x0000000001000000 : 0); case MISCREG_ID_AA64PFR1_EL1: return 0; // bits [63:0] RES0 (reserved for future use) diff --git a/src/arch/arm/isa.hh b/src/arch/arm/isa.hh index 736c395a7..8f2e0d26b 100644 --- a/src/arch/arm/isa.hh +++ b/src/arch/arm/isa.hh @@ -91,7 +91,6 @@ namespace ArmISA bool haveVirtualization; bool haveCrypto; bool haveLargeAsid64; - bool haveGICv3CPUInterface; uint8_t physAddrRange; bool haveSVE; bool haveLSE; @@ -746,14 +745,14 @@ namespace ArmISA Enums::DecoderFlavor decoderFlavor() const { return _decoderFlavor; } - /** Getter for haveGICv3CPUInterface */ + /** Returns true if the ISA has a GICv3 cpu interface */ bool haveGICv3CpuIfc() const { - // haveGICv3CPUInterface is initialized at startup time, hence + // gicv3CpuInterface is initialized at startup time, hence // trying to read its value before the startup stage will lead // to an error assert(afterStartup); - return haveGICv3CPUInterface; + return gicv3CpuInterface != nullptr; } Enums::VecRegRenameMode