From: Kenneth Graunke Date: Sun, 30 Nov 2014 09:41:15 +0000 (-0800) Subject: i965: Make Gen4-5 and Gen8+ ALT checks use ctx->_Shader too. X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d300e58db0db8e44bd430bfc22d612355e4aab31;p=mesa.git i965: Make Gen4-5 and Gen8+ ALT checks use ctx->_Shader too. Commit c0347705 changed the Gen6-7 code to use ctx->_Shader rather than ctx->Shader, but neglected to change the Gen4-5 or Gen8+ code. This might fix SSO related bugs, but ALT mode is only used for ARB programs, so if there's an actual problem, it's likely no one would run into it. Signed-off-by: Kenneth Graunke Reviewed-by: Ian Romanick Reviewed-by: Matt Turner --- diff --git a/src/mesa/drivers/dri/i965/brw_vs_state.c b/src/mesa/drivers/dri/i965/brw_vs_state.c index 998a22588c1..abd67718ccb 100644 --- a/src/mesa/drivers/dri/i965/brw_vs_state.c +++ b/src/mesa/drivers/dri/i965/brw_vs_state.c @@ -60,7 +60,7 @@ brw_upload_vs_unit(struct brw_context *brw) /* Use ALT floating point mode for ARB vertex programs, because they * require 0^0 == 1. */ - if (brw->ctx.Shader.CurrentProgram[MESA_SHADER_VERTEX] == NULL) + if (brw->ctx._Shader->CurrentProgram[MESA_SHADER_VERTEX] == NULL) vs->thread1.floating_point_mode = BRW_FLOATING_POINT_NON_IEEE_754; else vs->thread1.floating_point_mode = BRW_FLOATING_POINT_IEEE_754; diff --git a/src/mesa/drivers/dri/i965/brw_wm_state.c b/src/mesa/drivers/dri/i965/brw_wm_state.c index 12cbc72f41a..d2903c7cb45 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_state.c +++ b/src/mesa/drivers/dri/i965/brw_wm_state.c @@ -119,7 +119,7 @@ brw_upload_wm_unit(struct brw_context *brw) * rendering, CurrentProgram[MESA_SHADER_FRAGMENT] is used for this check * to differentiate between the GLSL and non-GLSL cases. */ - if (ctx->Shader.CurrentProgram[MESA_SHADER_FRAGMENT] == NULL) + if (ctx->_Shader->CurrentProgram[MESA_SHADER_FRAGMENT] == NULL) wm->thread1.floating_point_mode = BRW_FLOATING_POINT_NON_IEEE_754; else wm->thread1.floating_point_mode = BRW_FLOATING_POINT_IEEE_754; diff --git a/src/mesa/drivers/dri/i965/gen8_ps_state.c b/src/mesa/drivers/dri/i965/gen8_ps_state.c index 3aa0ef3502d..a3ce1d408d6 100644 --- a/src/mesa/drivers/dri/i965/gen8_ps_state.c +++ b/src/mesa/drivers/dri/i965/gen8_ps_state.c @@ -146,7 +146,7 @@ upload_ps_state(struct brw_context *brw) * rendering, CurrentFragmentProgram is used for this check to * differentiate between the GLSL and non-GLSL cases. */ - if (ctx->Shader.CurrentProgram[MESA_SHADER_FRAGMENT] == NULL) + if (ctx->_Shader->CurrentProgram[MESA_SHADER_FRAGMENT] == NULL) dw3 |= GEN7_PS_FLOATING_POINT_MODE_ALT; /* 3DSTATE_PS expects the number of threads per PSD, which is always 64; diff --git a/src/mesa/drivers/dri/i965/gen8_vs_state.c b/src/mesa/drivers/dri/i965/gen8_vs_state.c index 00f27314ca9..5a2021f8a29 100644 --- a/src/mesa/drivers/dri/i965/gen8_vs_state.c +++ b/src/mesa/drivers/dri/i965/gen8_vs_state.c @@ -42,7 +42,7 @@ upload_vs_state(struct brw_context *brw) /* Use ALT floating point mode for ARB vertex programs, because they * require 0^0 == 1. */ - if (ctx->Shader.CurrentProgram[MESA_SHADER_VERTEX] == NULL) + if (ctx->_Shader->CurrentProgram[MESA_SHADER_VERTEX] == NULL) floating_point_mode = GEN6_VS_FLOATING_POINT_MODE_ALT; BEGIN_BATCH(9);