From: Eddie Hung <eddieh@ece.ubc.ca>
Date: Tue, 19 Feb 2019 23:14:08 +0000 (-0800)
Subject: read_aiger to cope with non-unique POs
X-Git-Tag: working-ls180~1237^2~303
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d304882cba32cc9eb9be163fe6f24211bd39594a;p=yosys.git

read_aiger to cope with non-unique POs
---

diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc
index a1bdcbfff..941899316 100644
--- a/frontends/aiger/aigerparse.cc
+++ b/frontends/aiger/aigerparse.cc
@@ -650,12 +650,19 @@ void AigerReader::parse_aiger_binary()
         }
         else {
             log_debug("%d is an output\n", l1);
-            wire = createWireIfNotExists(module, l1);
-        }
-        if (wire->port_input) {
-            RTLIL::Wire *new_wire = module->addWire(NEW_ID);
-            module->connect(new_wire, wire);
-            wire = new_wire;
+            const unsigned variable = l1 >> 1;
+            const bool invert = l1 & 1;
+            RTLIL::IdString wire_name(stringf("\\n%d%s", variable, invert ? "_inv" : "")); // FIXME: is "_inv" the right suffix?
+            wire = module->wire(wire_name);
+            if (!wire)
+                wire = createWireIfNotExists(module, l1);
+            else {
+                if ((wire->port_input || wire->port_output)) {
+                    RTLIL::Wire *new_wire = module->addWire(stringf("\\o%zu", outputs.size()));
+                    module->connect(new_wire, wire);
+                    wire = new_wire;
+                }
+            }
         }
         wire->port_output = true;
         outputs.push_back(wire);