From: Alan Lawrence <alan.lawrence@arm.com>
Date: Tue, 15 Sep 2015 11:39:12 +0000 (+0000)
Subject: [AArch64 array_mode 1/8] Rename vec_store_lanes<mode>_lane to aarch64_vec_store_lanes... 
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d30ab8e0b79a37150f0bbcc8b0d7c390ee47f042;p=gcc.git

[AArch64 array_mode 1/8] Rename vec_store_lanes<mode>_lane to aarch64_vec_store_lanes<mode>_lane

	* config/aarch64/aarch64-simd.md (vec_store_lanesoi_lane<mode>): Rename
	to...
	(aarch64_vec_store_lanesoi_lane<mode>): ...this.

	(vec_store_lanesci_lane<mode>): Rename to...
	(aarch64_vec_store_lanesci_lane<mode>): ...this.

	(vec_store_lanesxi_lane<mode>): Rename to...
	(aarch64_vec_store_lanesxi_lane<mode>): ...this.

	(aarch64_st2_lane<mode>, aarch64_st3_lane<mode>,
	aarch64_st4_lane<mode>): Follow renaming.

From-SVN: r227781
---

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index be8089daa85..95e2d320947 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,18 @@
+2015-09-15  Alan Lawrence  <alan.lawrence@arm.com>
+
+	* config/aarch64/aarch64-simd.md (vec_store_lanesoi_lane<mode>): Rename
+	to...
+	(aarch64_vec_store_lanesoi_lane<mode>): ...this.
+
+	(vec_store_lanesci_lane<mode>): Rename to...
+	(aarch64_vec_store_lanesci_lane<mode>): ...this.
+
+	(vec_store_lanesxi_lane<mode>): Rename to...
+	(aarch64_vec_store_lanesxi_lane<mode>): ...this.
+
+	(aarch64_st2_lane<mode>, aarch64_st3_lane<mode>,
+	aarch64_st4_lane<mode>): Follow renaming.
+
 2015-09-15  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 
         * config/s390/s390.c (s390_const_operand_ok): Add missing
diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md
index a4eaecae2a0..67cb4c9bffd 100644
--- a/gcc/config/aarch64/aarch64-simd.md
+++ b/gcc/config/aarch64/aarch64-simd.md
@@ -3981,7 +3981,7 @@
 )
 
 ;; RTL uses GCC vector extension indices, so flip only for assembly.
-(define_insn "vec_store_lanesoi_lane<mode>"
+(define_insn "aarch64_vec_store_lanesoi_lane<mode>"
   [(set (match_operand:<V_TWO_ELEM> 0 "aarch64_simd_struct_operand" "=Utv")
 	(unspec:<V_TWO_ELEM> [(match_operand:OI 1 "register_operand" "w")
 		    (unspec:VALLDIF [(const_int 0)] UNSPEC_VSTRUCTDUMMY)
@@ -4079,7 +4079,7 @@
 )
 
 ;; RTL uses GCC vector extension indices, so flip only for assembly.
-(define_insn "vec_store_lanesci_lane<mode>"
+(define_insn "aarch64_vec_store_lanesci_lane<mode>"
   [(set (match_operand:<V_THREE_ELEM> 0 "aarch64_simd_struct_operand" "=Utv")
 	(unspec:<V_THREE_ELEM> [(match_operand:CI 1 "register_operand" "w")
 		    (unspec:VALLDIF [(const_int 0)] UNSPEC_VSTRUCTDUMMY)
@@ -4177,7 +4177,7 @@
 )
 
 ;; RTL uses GCC vector extension indices, so flip only for assembly.
-(define_insn "vec_store_lanesxi_lane<mode>"
+(define_insn "aarch64_vec_store_lanesxi_lane<mode>"
   [(set (match_operand:<V_FOUR_ELEM> 0 "aarch64_simd_struct_operand" "=Utv")
 	(unspec:<V_FOUR_ELEM> [(match_operand:XI 1 "register_operand" "w")
 		    (unspec:VALLDIF [(const_int 0)] UNSPEC_VSTRUCTDUMMY)
@@ -4886,7 +4886,9 @@
   machine_mode mode = <V_TWO_ELEM>mode;
   rtx mem = gen_rtx_MEM (mode, operands[0]);
 
-  emit_insn (gen_vec_store_lanesoi_lane<mode> (mem, operands[1], operands[2]));
+  emit_insn (gen_aarch64_vec_store_lanesoi_lane<mode> (mem,
+						       operands[1],
+						       operands[2]));
   DONE;
 })
 
@@ -4900,7 +4902,9 @@
   machine_mode mode = <V_THREE_ELEM>mode;
   rtx mem = gen_rtx_MEM (mode, operands[0]);
 
-  emit_insn (gen_vec_store_lanesci_lane<mode> (mem, operands[1], operands[2]));
+  emit_insn (gen_aarch64_vec_store_lanesci_lane<mode> (mem,
+						       operands[1],
+						       operands[2]));
   DONE;
 })
 
@@ -4914,7 +4918,9 @@
   machine_mode mode = <V_FOUR_ELEM>mode;
   rtx mem = gen_rtx_MEM (mode, operands[0]);
 
-  emit_insn (gen_vec_store_lanesxi_lane<mode> (mem, operands[1], operands[2]));
+  emit_insn (gen_aarch64_vec_store_lanesxi_lane<mode> (mem,
+						       operands[1],
+						       operands[2]));
   DONE;
 })