From: lkcl <lkcl@web>
Date: Thu, 17 Dec 2020 02:41:11 +0000 (+0000)
Subject: (no commit message)
X-Git-Tag: convert-csv-opcode-to-binary~1257
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d314bc806df0b9ebc9387c9e61c54fa39ae498a9;p=libreriscv.git

---

diff --git a/openpower/sv/svp_rewrite/svp64.mdwn b/openpower/sv/svp_rewrite/svp64.mdwn
index 862058cda..6b27fe87b 100644
--- a/openpower/sv/svp_rewrite/svp64.mdwn
+++ b/openpower/sv/svp_rewrite/svp64.mdwn
@@ -130,7 +130,7 @@ In the following table, `<N>` denotes the value of the corresponding register fi
 | 110       | Vector                 | `SVCR<N>_100` | `SV[F]R<N>_10`      |
 | 111       | Vector                 | `SVCR<N>_110` | `SV[F]R<N>_11`      |
 
-alternative which is understandable and, if EXTRA3 is zero, maps to "no effect" (scalar OpenPOWER ISA field naming)
+alternative which is understandable and, if EXTRA3 is zero, maps to "no effect" (scalar OpenPOWER ISA field naming).  also, these are the encodings used in the original SV Prefix scheme.  the reason why they were chosen is so that scalar registers in v3.0B and prefixed scalar registers have access to the same 32 registers.
 
 | R\*_EXTRA3 | Mode | CR Register   | Int/FP<br/>Register |
 |-----------|-------|---------------|---------------------|