From: mePy2 <mePy2@web>
Date: Sat, 27 Mar 2021 12:20:36 +0000 (+0000)
Subject: (no commit message)
X-Git-Tag: DRAFT_SVP64_0_1~1118
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d3167a174e8d814e57a3836f41e40b23445e6988;p=libreriscv.git

---

diff --git a/HDL_workflow.mdwn b/HDL_workflow.mdwn
index b2930a38f..1d0e64741 100644
--- a/HDL_workflow.mdwn
+++ b/HDL_workflow.mdwn
@@ -524,7 +524,7 @@ source hardware computer bus intended to let the parts of an integrated
 circuit communicate with each other.
 
 ## Coriolis2
-
+s [[mepy]]
 See [[HDL_workflow/coriolis2]] page, for those people doing layout work.
 
 ## Nextpnr