From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 23 May 2020 02:15:08 +0000 (+0100)
Subject: add b to CR pipe input data, for isel
X-Git-Tag: div_pipeline~925
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d32b9c50415c75374a8cc2c0184f059e60b46f36;p=soc.git

add b to CR pipe input data, for isel
---

diff --git a/src/soc/fu/cr/pipe_data.py b/src/soc/fu/cr/pipe_data.py
index 2894144f..599d2002 100644
--- a/src/soc/fu/cr/pipe_data.py
+++ b/src/soc/fu/cr/pipe_data.py
@@ -7,6 +7,7 @@ from soc.decoder.power_decoder2 import Data
 
 class CRInputData(IntegerData):
     regspec = [('INT', 'a', '0:63'),      # 64 bit range
+               ('INT', 'b', '0:63'),      # 6B bit range
                ('CR', 'full_cr', '0:31'), # 32 bit range
                ('CR', 'cr_a', '0:3'),     # 4 bit range
                ('CR', 'cr_b', '0:3'),     # 4 bit range
@@ -14,6 +15,7 @@ class CRInputData(IntegerData):
     def __init__(self, pspec):
         super().__init__(pspec)
         self.a = Signal(64, reset_less=True) # RA
+        self.b = Signal(64, reset_less=True) # RB
         self.full_cr = Signal(32, reset_less=True) # full CR in
         self.cr_a = Signal(4, reset_less=True)
         self.cr_b = Signal(4, reset_less=True)
@@ -22,6 +24,7 @@ class CRInputData(IntegerData):
     def __iter__(self):
         yield from super().__iter__()
         yield self.a
+        yield self.b
         yield self.full_cr
         yield self.cr_a
         yield self.cr_b
@@ -30,6 +33,7 @@ class CRInputData(IntegerData):
     def eq(self, i):
         lst = super().eq(i)
         return lst + [self.a.eq(i.a),
+                      self.b.eq(i.b),
                       self.full_cr.eq(i.full_cr),
                       self.cr_a.eq(i.cr_a),
                       self.cr_b.eq(i.cr_b),