From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Fri, 23 Nov 2018 17:33:53 +0000 (+0100)
Subject: soc/cores/spi_flash: add missing endianness parameter
X-Git-Tag: 24jan2021_ls180~1463
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d32e393033e2682b678bef225fc91be389544a13;p=litex.git

soc/cores/spi_flash: add missing endianness parameter
---

diff --git a/litex/soc/cores/spi_flash.py b/litex/soc/cores/spi_flash.py
index 86cab3ee..35d2ac44 100644
--- a/litex/soc/cores/spi_flash.py
+++ b/litex/soc/cores/spi_flash.py
@@ -117,7 +117,7 @@ class SpiFlashDualQuad(Module, AutoCSR):
 
 
 class SpiFlashSingle(Module, AutoCSR):
-    def __init__(self, pads, dummy=15, div=2):
+    def __init__(self, pads, dummy=15, div=2, endianness="big"):
         """
         Simple SPI flash.
         Supports 1-bit reads. Only supports mode0 (cpol=0, cpha=0).