From: Andrew Waterman Date: Fri, 4 May 2018 00:14:28 +0000 (-0700) Subject: C.LWSP and C.LDSP with rd=0 are legal instructions X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d336aee08ba9c5715d5d7836a39003e62ee4ada8;p=riscv-isa-sim.git C.LWSP and C.LDSP with rd=0 are legal instructions This mistake derives from an ambiguity in the specification that has since been corrected: https://github.com/riscv/riscv-isa-manual/commit/272d038abebe7f006ed7960b522f1e51890bb982 --- diff --git a/riscv/insns/c_flwsp.h b/riscv/insns/c_flwsp.h index 79058c4..d1e14fe 100644 --- a/riscv/insns/c_flwsp.h +++ b/riscv/insns/c_flwsp.h @@ -4,6 +4,5 @@ if (xlen == 32) { require_fp; WRITE_FRD(f32(MMU.load_uint32(RVC_SP + insn.rvc_lwsp_imm()))); } else { // c.ldsp - require(insn.rvc_rd() != 0); WRITE_RD(MMU.load_int64(RVC_SP + insn.rvc_ldsp_imm())); } diff --git a/riscv/insns/c_lwsp.h b/riscv/insns/c_lwsp.h index b3d74db..ed4dcf3 100644 --- a/riscv/insns/c_lwsp.h +++ b/riscv/insns/c_lwsp.h @@ -1,3 +1,2 @@ require_extension('C'); -require(insn.rvc_rd() != 0); WRITE_RD(MMU.load_int32(RVC_SP + insn.rvc_lwsp_imm()));