From: lkcl <lkcl@web>
Date: Tue, 20 Jul 2021 09:32:19 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: DRAFT_SVP64_0_1~605
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d33c294df7918a9427a408ea44c3bd802f864ab0;p=libreriscv.git

---

diff --git a/openpower/sv/setvl.mdwn b/openpower/sv/setvl.mdwn
index f77fde7db..52db48209 100644
--- a/openpower/sv/setvl.mdwn
+++ b/openpower/sv/setvl.mdwn
@@ -142,6 +142,8 @@ should be tested and placed into CR0.
 * setvl immediate = 4: test SVSTATE2
 * setvl immediate = 5: test SVSTATE3
 
+Testing any end condition of any loop of any REMAP state allows branches to be used to create loops
+
 # Pseudocode
 
     // instruction fields: