From: Jakub Jelinek Date: Fri, 5 Jan 2018 16:38:17 +0000 (+0100) Subject: re PR target/83604 (ICE in copy_to_mode_reg, at explow.c:630) X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d33e32a7236e05137aa5383a8585d26e482238ce;p=gcc.git re PR target/83604 (ICE in copy_to_mode_reg, at explow.c:630) PR target/83604 * config/i386/sse.md (VI248_VLBW): Rename to ... (VI248_AVX512VL): ... this. Don't guard V32HI with TARGET_AVX512BW. (vpshrd_, vpshld_, vpshrdv_, vpshrdv__mask, vpshrdv__maskz, vpshrdv__maskz_1, vpshldv_, vpshldv__mask, vpshldv__maskz, vpshldv__maskz_1): Use VI248_AVX512VL mode iterator instead of VI248_VLBW. * gcc.target/i386/pr83604.c: New test. From-SVN: r256280 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 3e48f38d073..e1042b89ddd 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,14 @@ +2018-01-05 Jakub Jelinek + + PR target/83604 + * config/i386/sse.md (VI248_VLBW): Rename to ... + (VI248_AVX512VL): ... this. Don't guard V32HI with TARGET_AVX512BW. + (vpshrd_, vpshld_, + vpshrdv_, vpshrdv__mask, vpshrdv__maskz, + vpshrdv__maskz_1, vpshldv_, vpshldv__mask, + vpshldv__maskz, vpshldv__maskz_1): Use VI248_AVX512VL + mode iterator instead of VI248_VLBW. + 2018-01-05 Jan Hubicka * ipa-fnsummary.c (record_modified_bb_info): Add OP. diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index b0ba91e6b84..0030a008e12 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -448,8 +448,8 @@ (define_mode_iterator VI2_AVX2_AVX512BW [(V32HI "TARGET_AVX512BW") (V16HI "TARGET_AVX2") V8HI]) -(define_mode_iterator VI248_VLBW - [(V32HI "TARGET_AVX512BW") V16SI V8DI +(define_mode_iterator VI248_AVX512VL + [V32HI V16SI V8DI (V16HI "TARGET_AVX512VL") (V8SI "TARGET_AVX512VL") (V4DI "TARGET_AVX512VL") (V8HI "TARGET_AVX512VL") (V4SI "TARGET_AVX512VL") (V2DI "TARGET_AVX512VL")]) @@ -20116,10 +20116,10 @@ (set_attr "mode" "")]) (define_insn "vpshrd_" - [(set (match_operand:VI248_VLBW 0 "register_operand" "=v") - (unspec:VI248_VLBW - [(match_operand:VI248_VLBW 1 "register_operand" "v") - (match_operand:VI248_VLBW 2 "nonimmediate_operand" "vm") + [(set (match_operand:VI248_AVX512VL 0 "register_operand" "=v") + (unspec:VI248_AVX512VL + [(match_operand:VI248_AVX512VL 1 "register_operand" "v") + (match_operand:VI248_AVX512VL 2 "nonimmediate_operand" "vm") (match_operand:SI 3 "const_0_to_255_operand" "n")] UNSPEC_VPSHRD))] "TARGET_AVX512VBMI2" @@ -20127,10 +20127,10 @@ [(set_attr ("prefix") ("evex"))]) (define_insn "vpshld_" - [(set (match_operand:VI248_VLBW 0 "register_operand" "=v") - (unspec:VI248_VLBW - [(match_operand:VI248_VLBW 1 "register_operand" "v") - (match_operand:VI248_VLBW 2 "nonimmediate_operand" "vm") + [(set (match_operand:VI248_AVX512VL 0 "register_operand" "=v") + (unspec:VI248_AVX512VL + [(match_operand:VI248_AVX512VL 1 "register_operand" "v") + (match_operand:VI248_AVX512VL 2 "nonimmediate_operand" "vm") (match_operand:SI 3 "const_0_to_255_operand" "n")] UNSPEC_VPSHLD))] "TARGET_AVX512VBMI2" @@ -20138,11 +20138,11 @@ [(set_attr ("prefix") ("evex"))]) (define_insn "vpshrdv_" - [(set (match_operand:VI248_VLBW 0 "register_operand" "=v") - (unspec:VI248_VLBW - [(match_operand:VI248_VLBW 1 "register_operand" "0") - (match_operand:VI248_VLBW 2 "register_operand" "v") - (match_operand:VI248_VLBW 3 "nonimmediate_operand" "vm")] + [(set (match_operand:VI248_AVX512VL 0 "register_operand" "=v") + (unspec:VI248_AVX512VL + [(match_operand:VI248_AVX512VL 1 "register_operand" "0") + (match_operand:VI248_AVX512VL 2 "register_operand" "v") + (match_operand:VI248_AVX512VL 3 "nonimmediate_operand" "vm")] UNSPEC_VPSHRDV))] "TARGET_AVX512VBMI2" "vpshrdv\t{%3, %2, %0|%0, %2, %3 }" @@ -20150,12 +20150,12 @@ (set_attr "mode" "")]) (define_insn "vpshrdv__mask" - [(set (match_operand:VI248_VLBW 0 "register_operand" "=v") - (vec_merge:VI248_VLBW - (unspec:VI248_VLBW - [(match_operand:VI248_VLBW 1 "register_operand" "0") - (match_operand:VI248_VLBW 2 "register_operand" "v") - (match_operand:VI248_VLBW 3 "nonimmediate_operand" "vm")] + [(set (match_operand:VI248_AVX512VL 0 "register_operand" "=v") + (vec_merge:VI248_AVX512VL + (unspec:VI248_AVX512VL + [(match_operand:VI248_AVX512VL 1 "register_operand" "0") + (match_operand:VI248_AVX512VL 2 "register_operand" "v") + (match_operand:VI248_AVX512VL 3 "nonimmediate_operand" "vm")] UNSPEC_VPSHRDV) (match_dup 1) (match_operand: 4 "register_operand" "Yk")))] @@ -20165,10 +20165,10 @@ (set_attr "mode" "")]) (define_expand "vpshrdv__maskz" - [(match_operand:VI248_VLBW 0 "register_operand") - (match_operand:VI248_VLBW 1 "register_operand") - (match_operand:VI248_VLBW 2 "register_operand") - (match_operand:VI248_VLBW 3 "nonimmediate_operand") + [(match_operand:VI248_AVX512VL 0 "register_operand") + (match_operand:VI248_AVX512VL 1 "register_operand") + (match_operand:VI248_AVX512VL 2 "register_operand") + (match_operand:VI248_AVX512VL 3 "nonimmediate_operand") (match_operand: 4 "register_operand")] "TARGET_AVX512VBMI2" { @@ -20180,14 +20180,14 @@ }) (define_insn "vpshrdv__maskz_1" - [(set (match_operand:VI248_VLBW 0 "register_operand" "=v") - (vec_merge:VI248_VLBW - (unspec:VI248_VLBW - [(match_operand:VI248_VLBW 1 "register_operand" "0") - (match_operand:VI248_VLBW 2 "register_operand" "v") - (match_operand:VI248_VLBW 3 "nonimmediate_operand" "vm")] + [(set (match_operand:VI248_AVX512VL 0 "register_operand" "=v") + (vec_merge:VI248_AVX512VL + (unspec:VI248_AVX512VL + [(match_operand:VI248_AVX512VL 1 "register_operand" "0") + (match_operand:VI248_AVX512VL 2 "register_operand" "v") + (match_operand:VI248_AVX512VL 3 "nonimmediate_operand" "vm")] UNSPEC_VPSHRDV) - (match_operand:VI248_VLBW 4 "const0_operand" "C") + (match_operand:VI248_AVX512VL 4 "const0_operand" "C") (match_operand: 5 "register_operand" "Yk")))] "TARGET_AVX512VBMI2" "vpshrdv\t{%3, %2, %0%{%5%}%{z%}|%0%{%5%}%{z%}, %2, %3 }" @@ -20195,11 +20195,11 @@ (set_attr "mode" "")]) (define_insn "vpshldv_" - [(set (match_operand:VI248_VLBW 0 "register_operand" "=v") - (unspec:VI248_VLBW - [(match_operand:VI248_VLBW 1 "register_operand" "0") - (match_operand:VI248_VLBW 2 "register_operand" "v") - (match_operand:VI248_VLBW 3 "nonimmediate_operand" "vm")] + [(set (match_operand:VI248_AVX512VL 0 "register_operand" "=v") + (unspec:VI248_AVX512VL + [(match_operand:VI248_AVX512VL 1 "register_operand" "0") + (match_operand:VI248_AVX512VL 2 "register_operand" "v") + (match_operand:VI248_AVX512VL 3 "nonimmediate_operand" "vm")] UNSPEC_VPSHLDV))] "TARGET_AVX512VBMI2" "vpshldv\t{%3, %2, %0|%0, %2, %3 }" @@ -20207,12 +20207,12 @@ (set_attr "mode" "")]) (define_insn "vpshldv__mask" - [(set (match_operand:VI248_VLBW 0 "register_operand" "=v") - (vec_merge:VI248_VLBW - (unspec:VI248_VLBW - [(match_operand:VI248_VLBW 1 "register_operand" "0") - (match_operand:VI248_VLBW 2 "register_operand" "v") - (match_operand:VI248_VLBW 3 "nonimmediate_operand" "vm")] + [(set (match_operand:VI248_AVX512VL 0 "register_operand" "=v") + (vec_merge:VI248_AVX512VL + (unspec:VI248_AVX512VL + [(match_operand:VI248_AVX512VL 1 "register_operand" "0") + (match_operand:VI248_AVX512VL 2 "register_operand" "v") + (match_operand:VI248_AVX512VL 3 "nonimmediate_operand" "vm")] UNSPEC_VPSHLDV) (match_dup 1) (match_operand: 4 "register_operand" "Yk")))] @@ -20222,10 +20222,10 @@ (set_attr "mode" "")]) (define_expand "vpshldv__maskz" - [(match_operand:VI248_VLBW 0 "register_operand") - (match_operand:VI248_VLBW 1 "register_operand") - (match_operand:VI248_VLBW 2 "register_operand") - (match_operand:VI248_VLBW 3 "nonimmediate_operand") + [(match_operand:VI248_AVX512VL 0 "register_operand") + (match_operand:VI248_AVX512VL 1 "register_operand") + (match_operand:VI248_AVX512VL 2 "register_operand") + (match_operand:VI248_AVX512VL 3 "nonimmediate_operand") (match_operand: 4 "register_operand")] "TARGET_AVX512VBMI2" { @@ -20237,14 +20237,14 @@ }) (define_insn "vpshldv__maskz_1" - [(set (match_operand:VI248_VLBW 0 "register_operand" "=v") - (vec_merge:VI248_VLBW - (unspec:VI248_VLBW - [(match_operand:VI248_VLBW 1 "register_operand" "0") - (match_operand:VI248_VLBW 2 "register_operand" "v") - (match_operand:VI248_VLBW 3 "nonimmediate_operand" "vm")] + [(set (match_operand:VI248_AVX512VL 0 "register_operand" "=v") + (vec_merge:VI248_AVX512VL + (unspec:VI248_AVX512VL + [(match_operand:VI248_AVX512VL 1 "register_operand" "0") + (match_operand:VI248_AVX512VL 2 "register_operand" "v") + (match_operand:VI248_AVX512VL 3 "nonimmediate_operand" "vm")] UNSPEC_VPSHLDV) - (match_operand:VI248_VLBW 4 "const0_operand" "C") + (match_operand:VI248_AVX512VL 4 "const0_operand" "C") (match_operand: 5 "register_operand" "Yk")))] "TARGET_AVX512VBMI2" "vpshldv\t{%3, %2, %0%{%5%}%{z%}|%0%{%5%}%{z%}, %2, %3 }" diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 2a18e22131f..685298befd2 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2018-01-05 Jakub Jelinek + + PR target/83604 + * gcc.target/i386/pr83604.c: New test. + 2018-01-05 Richard Sandiford * gcc.dg/vect/vect-align-4.c: New test. diff --git a/gcc/testsuite/gcc.target/i386/pr83604.c b/gcc/testsuite/gcc.target/i386/pr83604.c new file mode 100644 index 00000000000..c6ff2a406f5 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr83604.c @@ -0,0 +1,11 @@ +/* PR target/83604 */ +/* { dg-do compile } */ +/* { dg-options "-O2 -mno-avx" } */ + +typedef short V __attribute__((__vector_size__(64))); + +__attribute__((target ("avx512vbmi2"))) V +foo (V x, V y, V z) +{ + return __builtin_ia32_vpshrdv_v32hi (x, y, z); +}