From: Sebastien Bourdeauducq <sb@m-labs.hk>
Date: Fri, 13 Mar 2015 23:27:24 +0000 (+0100)
Subject: mibuild/xilinx: remove obsolete CRG_DS
X-Git-Tag: 24jan2021_ls180~2099^2~189
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d34b7d7a6b1832fa74373cade6009baf0da67070;p=litex.git

mibuild/xilinx: remove obsolete CRG_DS
---

diff --git a/mibuild/xilinx/common.py b/mibuild/xilinx/common.py
index 9b5d9943..a7b1175c 100644
--- a/mibuild/xilinx/common.py
+++ b/mibuild/xilinx/common.py
@@ -29,22 +29,6 @@ def settings(path, ver=None, sub=None):
 
 	raise OSError("no settings file found")
 
-class CRG_DS(Module):
-	def __init__(self, platform, clk_name, rst_name, rst_invert=False):
-		reset_less = rst_name is None
-		self.clock_domains.cd_sys = ClockDomain(reset_less=reset_less)
-		self._clk = platform.request(clk_name)
-		self.specials += Instance("IBUFGDS",
-			Instance.Input("I", self._clk.p),
-			Instance.Input("IB", self._clk.n),
-			Instance.Output("O", self.cd_sys.clk)
-		)
-		if not reset_less:
-			if rst_invert:
-				self.comb += self.cd_sys.rst.eq(~platform.request(rst_name))
-			else:
-				self.comb += self.cd_sys.rst.eq(platform.request(rst_name))
-
 class XilinxNoRetimingImpl(Module):
 	def __init__(self, reg):
 		self.specials += SynthesisDirective("attribute register_balancing of {r} is no", r=reg)