From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Fri, 29 Jan 2021 14:59:49 +0000 (+0000)
Subject: add SV etype/ptype to power decoder
X-Git-Tag: convert-csv-opcode-to-binary~297
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d351455aa31a6b9383a3eee69d68eff3d40fe5a6;p=soc.git

add SV etype/ptype to power decoder
---

diff --git a/src/soc/decoder/power_decoder.py b/src/soc/decoder/power_decoder.py
index 6443fd68..2b01d4d4 100644
--- a/src/soc/decoder/power_decoder.py
+++ b/src/soc/decoder/power_decoder.py
@@ -92,6 +92,7 @@ from nmigen import Module, Elaboratable, Signal, Cat, Mux
 from nmigen.cli import rtlil
 from soc.decoder.power_enums import (Function, Form, MicrOp,
                                      In1Sel, In2Sel, In3Sel, OutSel,
+                                     SVEtype, SVPtype, # Simple-V
                                      RC, LdstLen, LDSTMode, CryIn,
                                      single_bit_flags, CRInSel,
                                      CROutSel, get_signal_name,
@@ -118,6 +119,8 @@ power_op_types = {'function_unit': Function,
                   'internal_op': MicrOp,
                   'form': Form,
                   'asmcode': 8,
+                  'SV_Etype': SVEtype,
+                  'SV_Ptype': SVPtype,
                   'in1_sel': In1Sel,
                   'in2_sel': In2Sel,
                   'in3_sel': In3Sel,