From: lkcl <lkcl@web>
Date: Sat, 18 Jun 2022 11:14:53 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~1722
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d35f12fcbced4cd46fce3f0d496a873c2c7cc144;p=libreriscv.git

---

diff --git a/openpower/sv.mdwn b/openpower/sv.mdwn
index 07048b15f..c6ad546f8 100644
--- a/openpower/sv.mdwn
+++ b/openpower/sv.mdwn
@@ -147,7 +147,7 @@ Pages being developed and examples
     behaviour: All/Some Vector CRs
   - For arithmetic and logical, see [[sv/normal]]
   - [[sv/mv.vec]] pack/unpack move to and from vec2/3/4,
-    actually an RM.EXTRA Mode and a [[sv/remap] mode
+    actually an RM.EXTRA Mode and a [[sv/remap]] mode
 
 Core SVP64 instructions: