From: Jason Ekstrand Date: Wed, 5 Apr 2017 23:59:06 +0000 (-0700) Subject: intel/blorp: Emit 3DSTATE_STENCIL_BUFFER before HIER_DEPTH X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d3785dcb2f65771f32ee32532fc4ff5c1aa3e952;p=mesa.git intel/blorp: Emit 3DSTATE_STENCIL_BUFFER before HIER_DEPTH We're about to replace blorp's emit code with ISL and it emits them in the other order. This makes diffing the aubs easier. Reviewed-by: Topi Pohjolainen --- diff --git a/src/intel/blorp/blorp_genX_exec.h b/src/intel/blorp/blorp_genX_exec.h index 379146245d9..9532e89b12f 100644 --- a/src/intel/blorp/blorp_genX_exec.h +++ b/src/intel/blorp/blorp_genX_exec.h @@ -854,18 +854,6 @@ blorp_emit_depth_stencil_config(struct blorp_batch *batch, } } - blorp_emit(batch, GENX(3DSTATE_HIER_DEPTH_BUFFER), hiz) { - if (params->depth.aux_usage == ISL_AUX_USAGE_HIZ) { - hiz.SurfacePitch = params->depth.aux_surf.row_pitch - 1; - hiz.SurfaceBaseAddress = params->depth.aux_addr; - hiz.HierarchicalDepthBufferMOCS = mocs; -#if GEN_GEN >= 8 - hiz.SurfaceQPitch = - isl_surf_get_array_pitch_sa_rows(¶ms->depth.aux_surf) >> 2; -#endif - } - } - blorp_emit(batch, GENX(3DSTATE_STENCIL_BUFFER), sb) { if (params->stencil.enabled) { #if GEN_GEN >= 8 || GEN_IS_HASWELL @@ -883,6 +871,18 @@ blorp_emit_depth_stencil_config(struct blorp_batch *batch, } } + blorp_emit(batch, GENX(3DSTATE_HIER_DEPTH_BUFFER), hiz) { + if (params->depth.aux_usage == ISL_AUX_USAGE_HIZ) { + hiz.SurfacePitch = params->depth.aux_surf.row_pitch - 1; + hiz.SurfaceBaseAddress = params->depth.aux_addr; + hiz.HierarchicalDepthBufferMOCS = mocs; +#if GEN_GEN >= 8 + hiz.SurfaceQPitch = + isl_surf_get_array_pitch_sa_rows(¶ms->depth.aux_surf) >> 2; +#endif + } + } + /* 3DSTATE_CLEAR_PARAMS * * From the Sandybridge PRM, Volume 2, Part 1, Section 3DSTATE_CLEAR_PARAMS: