From: Miodrag Milanovic <mmicko@gmail.com>
Date: Fri, 4 Oct 2019 06:24:37 +0000 (+0200)
Subject: Removed alu and div_mod test as agreed, ignore generated files
X-Git-Tag: working-ls180~990^2~9
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d37cd267a56295737e95f5bc5e6f446c27605639;p=yosys.git

Removed alu and div_mod test as agreed, ignore generated files
---

diff --git a/tests/xilinx/.gitignore b/tests/xilinx/.gitignore
index 54733fb71..89879f209 100644
--- a/tests/xilinx/.gitignore
+++ b/tests/xilinx/.gitignore
@@ -2,3 +2,4 @@
 /*.out
 /run-test.mk
 /*_uut.v
+/test_macc
\ No newline at end of file
diff --git a/tests/xilinx/alu.v b/tests/xilinx/alu.v
deleted file mode 100644
index f82cc2e21..000000000
--- a/tests/xilinx/alu.v
+++ /dev/null
@@ -1,19 +0,0 @@
-module top (
-	input clock,
-	input [31:0] dinA, dinB,
-	input [2:0] opcode,
-	output reg [31:0] dout
-);
-	always @(posedge clock) begin
-		case (opcode)
-		0: dout <= dinA + dinB;
-		1: dout <= dinA - dinB;
-		2: dout <= dinA >> dinB;
-		3: dout <= $signed(dinA) >>> dinB;
-		4: dout <= dinA << dinB;
-		5: dout <= dinA & dinB;
-		6: dout <= dinA | dinB;
-		7: dout <= dinA ^ dinB;
-		endcase
-	end
-endmodule
diff --git a/tests/xilinx/alu.ys b/tests/xilinx/alu.ys
deleted file mode 100644
index f85f03928..000000000
--- a/tests/xilinx/alu.ys
+++ /dev/null
@@ -1,21 +0,0 @@
-read_verilog alu.v
-hierarchy -top top
-proc
-flatten
-equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
-design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
-cd top # Constrain all select calls below inside the top module
-
-
-select -assert-count 1 t:BUFG
-select -assert-count 32 t:LUT1
-select -assert-count 142 t:LUT2
-select -assert-count 55  t:LUT3
-select -assert-count 70  t:LUT4
-select -assert-count 46  t:LUT5
-select -assert-count 625 t:LUT6
-select -assert-count 62 t:MUXCY
-select -assert-count 265  t:MUXF7
-select -assert-count 79  t:MUXF8
-select -assert-count 64 t:XORCY
-select -assert-none t:BUFG t:FDRE t:LUT1 t:LUT2 t:LUT3 t:LUT4 t:LUT5 t:LUT6 t:MUXCY t:MUXF7 t:MUXF8 t:XORCY %% t:* %D
diff --git a/tests/xilinx/div_mod.v b/tests/xilinx/div_mod.v
deleted file mode 100644
index 64a36707d..000000000
--- a/tests/xilinx/div_mod.v
+++ /dev/null
@@ -1,13 +0,0 @@
-module top
-(
- input [3:0] x,
- input [3:0] y,
-
- output [3:0] A,
- output [3:0] B
- );
-
-assign A =  x % y;
-assign B =  x / y;
-
-endmodule
diff --git a/tests/xilinx/div_mod.ys b/tests/xilinx/div_mod.ys
deleted file mode 100644
index da7e60a9a..000000000
--- a/tests/xilinx/div_mod.ys
+++ /dev/null
@@ -1,17 +0,0 @@
-read_verilog div_mod.v
-hierarchy -top top
-flatten
-equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
-design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
-cd top # Constrain all select calls below inside the top module
-
-select -assert-count 12 t:LUT1
-select -assert-count 19 t:LUT2
-select -assert-count 13 t:LUT4
-select -assert-count 6  t:LUT5
-select -assert-count 82 t:LUT6
-select -assert-count 65 t:MUXCY
-select -assert-count 37 t:MUXF7
-select -assert-count 11 t:MUXF8
-select -assert-count 28 t:XORCY
-select -assert-none t:LUT1 t:LUT2 t:LUT4 t:LUT5 t:LUT6 t:MUXCY t:MUXF7 t:MUXF8 t:XORCY %% t:* %D