From: Richard Kenner <kenner@gcc.gnu.org>
Date: Tue, 3 Mar 1992 23:36:58 +0000 (-0500)
Subject: *** empty log message ***
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d38cfc1e108696c2c26040c2147ca49be338bed1;p=gcc.git

*** empty log message ***

From-SVN: r387
---

diff --git a/gcc/config/vax/vax.h b/gcc/config/vax/vax.h
index a26f286b459..9b8cf5c23b4 100644
--- a/gcc/config/vax/vax.h
+++ b/gcc/config/vax/vax.h
@@ -283,6 +283,16 @@ enum reg_class { NO_REGS, ALL_REGS, LIM_REG_CLASSES };
 		 || (VALUE) == CONST0_RTX (SFmode))	\
    : 0)
 
+/* Optional extra constraints for this machine.
+
+   For the VAX, `Q' means that OP is a MEM that does not have a mode-dependent
+   address.  */
+
+#define EXTRA_CONSTRAINT(OP, C) \
+  ((C) == 'Q'								\
+   ? GET_CODE (OP) == MEM && ! mode_dependent_address_p (XEXP (OP, 0))	\
+   : 0)
+
 /* Given an rtx X being reloaded into a reg required to be
    in class CLASS, return the class of reg to actually use.
    In general this is just CLASS; but on some machines
diff --git a/gcc/config/vax/vax.md b/gcc/config/vax/vax.md
index be1b3b0ff23..e17c8cadb91 100644
--- a/gcc/config/vax/vax.md
+++ b/gcc/config/vax/vax.md
@@ -1465,13 +1465,14 @@
   "j%C0 %l1") ; %C0 negates condition
 
 ;; Recognize jbs, jlbs, jbc and jlbc instructions.  Note that the operand
-;; if this insn is SImode in the hardware.  However, if it is memory,
-;; we use QImode.  So we can't allow the memory address to be indexed.
+;; of jlbs and jlbc insns are SImode in the hardware.  However, if it is
+;; memory, we use QImode in the insn.  So we can't use those instructions
+;; for mode-dependent addresses.
 
 (define_insn ""
   [(set (pc)
 	(if_then_else
-	 (ne (zero_extract:SI (match_operand:QI 0 "reg_or_nxmem_operand" "g,g")
+	 (ne (zero_extract:SI (match_operand:QI 0 "nonimmediate_operand" "rQ,g")
 			      (const_int 1)
 			      (match_operand:SI 1 "general_operand" "I,g"))
 	     (const_int 0))
@@ -1485,7 +1486,7 @@
 (define_insn ""
   [(set (pc)
 	(if_then_else
-	 (eq (zero_extract:SI (match_operand:QI 0 "reg_or_nxmem_operand" "g,g")
+	 (eq (zero_extract:SI (match_operand:QI 0 "nonimmediate_operand" "rQ,g")
 			      (const_int 1)
 			      (match_operand:SI 1 "general_operand" "I,g"))
 	     (const_int 0))