From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 2 May 2019 01:23:21 +0000 (-0700)
Subject: Back to passing all xc7srl tests!
X-Git-Tag: yosys-0.9~161^2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d394b9301b2619b8cb64f9faea4c112bf2a07925;p=yosys.git

Back to passing all xc7srl tests!
---

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index dbafec301..8aa7b508e 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -205,17 +205,16 @@ struct SynthXilinxPass : public ScriptPass
 		}
 
 		if (check_label("fine")) {
-			run("opt -fast");
-			run("memory_map");
-			run("dffsr2dff");
-			run("dff2dffe");
-
 			// shregmap -tech xilinx can cope with $shiftx and $mux
 			//   cells for identifiying variable-length shift registers,
 			//   so attempt to convert $pmux-es to the former
 			if (!nosrl || help_mode)
 				run("pmux2shiftx", "(skip if '-nosrl')");
 
+			run("opt -fast -full");
+			run("memory_map");
+			run("dffsr2dff");
+			run("dff2dffe");
 			run("opt -full");
 
 			if (!vpr || help_mode)