From: Luke Kenneth Casson Leighton Date: Mon, 12 Feb 2024 17:51:50 +0000 (+0000) Subject: bug 1244: add assembler and python maxloc listing to slides X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d397b961755f3f18802ca9722f9455ca5e4ee426;p=libreriscv.git bug 1244: add assembler and python maxloc listing to slides --- diff --git a/conferences/fosdem2024/fosdem2024_ddffirst/fosdem2024_ddffirst.tex b/conferences/fosdem2024/fosdem2024_ddffirst/fosdem2024_ddffirst.tex index 3317021a8..fdbc83369 100644 --- a/conferences/fosdem2024/fosdem2024_ddffirst/fosdem2024_ddffirst.tex +++ b/conferences/fosdem2024/fosdem2024_ddffirst/fosdem2024_ddffirst.tex @@ -217,11 +217,19 @@ for (i = 0; i < VL; i++) } \frame{\frametitle{maxloc} + \lstinputlisting[language={}]{maxloc.py} + \begin{itemize} \item "TODO \end{itemize} } +\frame{\frametitle{maxlocassembler} + + \lstinputlisting[language={}]{maxloc.s} + +} + \frame{\frametitle{Summary} \begin{itemize} diff --git a/conferences/fosdem2024/fosdem2024_ddffirst/maxloc.py b/conferences/fosdem2024/fosdem2024_ddffirst/maxloc.py index 031ffc33d..e596151f8 100644 --- a/conferences/fosdem2024/fosdem2024_ddffirst/maxloc.py +++ b/conferences/fosdem2024/fosdem2024_ddffirst/maxloc.py @@ -1,4 +1,3 @@ - m,nm,i,n = 0,0,0,len(a) while (im): -sv.minmax./ff=le/m=ge/mr 4,*10,4,1 # r4 accumulator -crternlogi 0,1,2,127 # test greater/equal or VL=0 -sv.crand *19,*16,0 # clear if CR0.eq=0 -# nm = i (count masked bits. could use crweirds here) -sv.svstep/mr/m=so 1,0,6,1 # svstep: get vector dststep -sv.creqv *16,*16,*16 # set mask on already-tested -bc 12,0, -0x40 # CR0 lt bit clear, branch back +sv.creqv *16,*16,*16 # set mask on already-tested +setvl 2,0,4,0,1,1 # set MVL=4,VL=MIN(MVL,CTR) +mtcrf 128,0 # clear CR0 (in case VL=0?) +# while (im): +sv.minmax./ff=le/m=ge/mr 4,*10,4,1 # r4 accumulate +crternlogi 0,1,2,127 # test >= (or VL=0) +sv.crand *19,*16,0 # clear if CR0.eq=0 +# nm = i: count masked bits. could use crweirds +sv.svstep/mr/m=so 1,0,6,1 # get vector dststep +sv.creqv *16,*16,*16 # set mask on already-tested +bc 12,0,-0x40 # CR0 lt clear, branch back