From: bugzilla-daemon <bugzilla-daemon@libre-soc.org>
Date: Thu, 9 Apr 2020 13:46:31 +0000 (+0000)
Subject: [libre-riscv-dev] [Bug 186] Create decoder for SOC: Power ISA and RISC-V
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d397daed83bcf1d9d3c3caa03e769b65db676354;p=libre-riscv-dev.git

[libre-riscv-dev] [Bug 186] Create decoder for SOC: Power ISA and RISC-V
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+Date: Thu, 09 Apr 2020 13:46:31 +0000
+X-Bugzilla-Reason: CC
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+X-Bugzilla-Product: Libre-SOC's first SoC
+X-Bugzilla-Component: Specification
+X-Bugzilla-Version: unspecified
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+X-Bugzilla-Severity: enhancement
+X-Bugzilla-Who: libre-soc@platen-software.de
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+X-Bugzilla-Priority: ---
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+Message-ID: <bug-186-13-e3nvNrK4mN@https.bugs.libre-soc.org/>
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+Subject: [libre-riscv-dev] [Bug 186] Create decoder for SOC: Power ISA and
+ RISC-V
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