From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Fri, 26 Jun 2020 23:26:58 +0000 (+0100)
Subject: whitespace and imports
X-Git-Tag: div_pipeline~244
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d39e4a9affef4b79ef3d13813afdb1ecbeaf0bd4;p=soc.git

whitespace and imports
---

diff --git a/src/soc/minerva/units/fetch.py b/src/soc/minerva/units/fetch.py
index a090185e..f4cb3fb7 100644
--- a/src/soc/minerva/units/fetch.py
+++ b/src/soc/minerva/units/fetch.py
@@ -1,8 +1,8 @@
 from nmigen import Elaboratable, Module, Signal, Record, Const, Mux
 from nmigen.utils import log2_int
 
-from ..cache import L1Cache
-from ..wishbone import wishbone_layout, WishboneArbiter, Cycle
+from soc.minerva.cache import L1Cache
+from soc.minerva.wishbone import wishbone_layout, WishboneArbiter, Cycle
 
 
 __all__ = ["PCSelector", "FetchUnitInterface", "BareFetchUnit",
@@ -130,7 +130,8 @@ class CachedFetchUnit(FetchUnitInterface, Elaboratable):
         a_icache_select = Signal()
         f_icache_select = Signal()
 
-        m.d.comb += a_icache_select.eq((self.a_pc >= icache.base) & (self.a_pc < icache.limit))
+        m.d.comb += a_icache_select.eq((self.a_pc >= icache.base) &
+                                        (self.a_pc < icache.limit))
         with m.If(~self.a_stall):
             m.d.sync += f_icache_select.eq(a_icache_select)