From: Gabe Black Date: Thu, 21 Jan 2021 11:49:07 +0000 (-0800) Subject: arch-arm: Stop "using namespace std" X-Git-Tag: develop-gem5-snapshot~240 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d3a4662a145bd4a08c733c2453dc0ddde22eaeed;p=gem5.git arch-arm: Stop "using namespace std" Change-Id: If0f373bdaadce81c5ebbc37b03810335c42dd10a Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39561 Reviewed-by: Giacomo Travaglini Maintainer: Giacomo Travaglini Tested-by: kokoro --- diff --git a/src/arch/arm/insts/macromem.cc b/src/arch/arm/insts/macromem.cc index 1ce9705e6..e20aef941 100644 --- a/src/arch/arm/insts/macromem.cc +++ b/src/arch/arm/insts/macromem.cc @@ -45,7 +45,6 @@ #include "arch/arm/generated/decoder.hh" #include "arch/arm/insts/neon64_mem.hh" -using namespace std; using namespace ArmISAInst; namespace ArmISA diff --git a/src/arch/arm/insts/mem.cc b/src/arch/arm/insts/mem.cc index e44fc9614..8ee3f4929 100644 --- a/src/arch/arm/insts/mem.cc +++ b/src/arch/arm/insts/mem.cc @@ -42,8 +42,6 @@ #include "base/loader/symtab.hh" -using namespace std; - namespace ArmISA { @@ -75,10 +73,10 @@ MemoryReg::printOffset(std::ostream &os) const } } -string +std::string RfeOp::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const { - stringstream ss; + std::stringstream ss; switch (mode) { case DecrementAfter: printMnemonic(ss, "da"); @@ -100,10 +98,10 @@ RfeOp::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const return ss.str(); } -string +std::string SrsOp::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const { - stringstream ss; + std::stringstream ss; switch (mode) { case DecrementAfter: printMnemonic(ss, "da"); diff --git a/src/arch/arm/insts/mem64.cc b/src/arch/arm/insts/mem64.cc index ed159beca..44fe7357b 100644 --- a/src/arch/arm/insts/mem64.cc +++ b/src/arch/arm/insts/mem64.cc @@ -41,8 +41,6 @@ #include "base/loader/symtab.hh" #include "mem/request.hh" -using namespace std; - namespace ArmISA { diff --git a/src/arch/arm/linux/process.cc b/src/arch/arm/linux/process.cc index 7f86c24fe..cba3d147a 100644 --- a/src/arch/arm/linux/process.cc +++ b/src/arch/arm/linux/process.cc @@ -54,7 +54,6 @@ #include "sim/syscall_emul.hh" #include "sim/system.hh" -using namespace std; using namespace ArmISA; const Addr ArmLinuxProcess32::commPage = 0xffff0000; diff --git a/src/arch/arm/miscregs.cc b/src/arch/arm/miscregs.cc index b5af9b659..5dfbd4827 100644 --- a/src/arch/arm/miscregs.cc +++ b/src/arch/arm/miscregs.cc @@ -333,8 +333,6 @@ decodeCP14Reg(unsigned crn, unsigned opc1, unsigned crm, unsigned opc2) return MISCREG_CP14_UNIMPL; } -using namespace std; - MiscRegIndex decodeCP15Reg(unsigned crn, unsigned opc1, unsigned crm, unsigned opc2) { @@ -3393,7 +3391,7 @@ decodeAArch64SysReg(unsigned op0, unsigned op1, return MISCREG_UNKNOWN; } -bitset miscRegInfo[NUM_MISCREGS]; // initialized below +std::bitset miscRegInfo[NUM_MISCREGS]; // initialized below void ISA::initializeMiscRegMetadata() diff --git a/src/arch/arm/pauth_helpers.cc b/src/arch/arm/pauth_helpers.cc index 7424eb3c9..aa9338417 100644 --- a/src/arch/arm/pauth_helpers.cc +++ b/src/arch/arm/pauth_helpers.cc @@ -41,7 +41,6 @@ #include "base/bitfield.hh" using namespace ArmISA; -using namespace std; bool ArmISA::calculateTBI(ThreadContext* tc, ExceptionLevel el, @@ -101,11 +100,11 @@ ArmISA::calculateBottomPACBit(ThreadContext* tc, ExceptionLevel el, using64k = el == EL2 ? tcr2.tg0 == 0x1 : tcr3.tg0 == 0x1 ; } uint32_t max_limit_tsz_field = using64k ? 47 : 48; - tsz_field = min(tsz_field, max_limit_tsz_field); + tsz_field = std::min(tsz_field, max_limit_tsz_field); const AA64MMFR2 mm_fr2 = tc->readMiscReg(MISCREG_ID_AA64MMFR2_EL1); uint32_t tszmin = (using64k && (bool)mm_fr2.varange) ? 12 : 16; - tsz_field = max(tsz_field, tszmin); + tsz_field = std::max(tsz_field, tszmin); return (64-tsz_field); } diff --git a/src/arch/arm/process.cc b/src/arch/arm/process.cc index 6f37d1196..86bc8e211 100644 --- a/src/arch/arm/process.cc +++ b/src/arch/arm/process.cc @@ -55,7 +55,6 @@ #include "sim/syscall_return.hh" #include "sim/system.hh" -using namespace std; using namespace ArmISA; ArmProcess::ArmProcess(const ProcessParams ¶ms, @@ -78,9 +77,9 @@ ArmProcess32::ArmProcess32(const ProcessParams ¶ms, Addr next_thread_stack_base = stack_base - max_stack_size; Addr mmap_end = 0x40000000L; - memState = make_shared(this, brk_point, stack_base, - max_stack_size, next_thread_stack_base, - mmap_end); + memState = std::make_shared( + this, brk_point, stack_base, max_stack_size, + next_thread_stack_base, mmap_end); } ArmProcess64::ArmProcess64( @@ -94,9 +93,9 @@ ArmProcess64::ArmProcess64( Addr next_thread_stack_base = stack_base - max_stack_size; Addr mmap_end = 0x4000000000L; - memState = make_shared(this, brk_point, stack_base, - max_stack_size, next_thread_stack_base, - mmap_end); + memState = std::make_shared( + this, brk_point, stack_base, max_stack_size, + next_thread_stack_base, mmap_end); } void @@ -257,7 +256,7 @@ ArmProcess::argsInit(int pageSize, IntRegIndex spIndex) std::vector> auxv; - string filename; + std::string filename; if (argv.size() < 1) filename = ""; else @@ -318,7 +317,7 @@ ArmProcess::argsInit(int pageSize, IntRegIndex spIndex) // A sentry NULL void pointer at the top of the stack. int sentry_size = intSize; - string platform = "v71"; + std::string platform = "v71"; int platform_size = platform.size() + 1; // Bytes for AT_RANDOM above, we'll just keep them 0 diff --git a/src/arch/arm/qarma.cc b/src/arch/arm/qarma.cc index 4e18b7de2..5805709cf 100644 --- a/src/arch/arm/qarma.cc +++ b/src/arch/arm/qarma.cc @@ -42,7 +42,6 @@ #include "base/bitfield.hh" using namespace QARMA; -using namespace std; uint8_t diff --git a/src/arch/arm/remote_gdb.cc b/src/arch/arm/remote_gdb.cc index 4d4915b73..96344a97d 100644 --- a/src/arch/arm/remote_gdb.cc +++ b/src/arch/arm/remote_gdb.cc @@ -163,7 +163,6 @@ #include "sim/full_system.hh" #include "sim/system.hh" -using namespace std; using namespace ArmISA; static bool diff --git a/src/arch/arm/self_debug.cc b/src/arch/arm/self_debug.cc index e55df64ad..86e4ae52d 100644 --- a/src/arch/arm/self_debug.cc +++ b/src/arch/arm/self_debug.cc @@ -42,7 +42,6 @@ #include "base/bitfield.hh" using namespace ArmISA; -using namespace std; Fault SelfDebug::testDebug(ThreadContext *tc, const RequestPtr &req, diff --git a/src/arch/arm/system.cc b/src/arch/arm/system.cc index bda5ed253..7f5fa1313 100644 --- a/src/arch/arm/system.cc +++ b/src/arch/arm/system.cc @@ -51,7 +51,6 @@ #include "dev/arm/gic_v2.hh" #include "mem/physical.hh" -using namespace std; using namespace Linux; using namespace ArmISA; diff --git a/src/arch/arm/tlb.cc b/src/arch/arm/tlb.cc index 91c70884e..6f16f6cf7 100644 --- a/src/arch/arm/tlb.cc +++ b/src/arch/arm/tlb.cc @@ -71,7 +71,6 @@ #include "sim/process.hh" #include "sim/pseudo_inst.hh" -using namespace std; using namespace ArmISA; TLB::TLB(const ArmTLBParams &p) diff --git a/src/arch/arm/tracers/tarmac_parser.cc b/src/arch/arm/tracers/tarmac_parser.cc index cdb24cac0..6521b2737 100644 --- a/src/arch/arm/tracers/tarmac_parser.cc +++ b/src/arch/arm/tracers/tarmac_parser.cc @@ -54,7 +54,6 @@ #include "sim/faults.hh" #include "sim/sim_exit.hh" -using namespace std; using namespace ArmISA; namespace Trace { @@ -68,7 +67,8 @@ TarmacParserRecord::ParserRegEntry TarmacParserRecord::regRecord; TarmacParserRecord::ParserMemEntry TarmacParserRecord::memRecord; TarmacBaseRecord::TarmacRecordType TarmacParserRecord::currRecordType; -list TarmacParserRecord::destRegRecords; +std::list + TarmacParserRecord::destRegRecords; char TarmacParserRecord::buf[TarmacParserRecord::MaxLineLength]; TarmacParserRecord::MiscRegMap TarmacParserRecord::miscRegMap = { @@ -737,10 +737,10 @@ TarmacParserRecord::MiscRegMap TarmacParserRecord::miscRegMap = { void TarmacParserRecord::TarmacParserRecordEvent::process() { - ostream &outs = Trace::output(); + std::ostream &outs = Trace::output(); - list::iterator it = destRegRecords.begin(), - end = destRegRecords.end(); + std::list::iterator it = destRegRecords.begin(), + end = destRegRecords.end(); std::vector values; @@ -915,14 +915,14 @@ TarmacParserRecord::TarmacParserRecordEvent::process() TarmacParserRecord::printMismatchHeader(inst, pc); mismatch = true; } - outs << "diff> [" << it->repr << "] gem5: 0x" << hex; + outs << "diff> [" << it->repr << "] gem5: 0x" << std::hex; for (auto v : values) - outs << setw(16) << setfill('0') << v; + outs << std::setw(16) << std::setfill('0') << v; - outs << ", TARMAC: 0x" << hex; + outs << ", TARMAC: 0x" << std::hex; for (auto v : it->values) - outs << setw(16) << setfill('0') << v; - outs << endl; + outs << std::setw(16) << std::setfill('0') << v; + outs << std::endl; } } destRegRecords.clear(); @@ -947,14 +947,14 @@ void TarmacParserRecord::printMismatchHeader(const StaticInstPtr staticInst, ArmISA::PCState pc) { - ostream &outs = Trace::output(); - outs << "\nMismatch between gem5 and TARMAC trace @ " << dec << curTick() - << " ticks\n" - << "[seq_num: " << dec << instRecord.seq_num - << ", opcode: 0x" << hex << (staticInst->machInst & 0xffffffff) + std::ostream &outs = Trace::output(); + outs << "\nMismatch between gem5 and TARMAC trace @ " << std::dec + << curTick() << " ticks\n" + << "[seq_num: " << std::dec << instRecord.seq_num + << ", opcode: 0x" << std::hex << (staticInst->machInst & 0xffffffff) << ", PC: 0x" << pc.pc() << ", disasm: " << staticInst->disassemble(pc.pc()) << "]" - << endl; + << std::endl; } TarmacParserRecord::TarmacParserRecord(Tick _when, ThreadContext *_thread, @@ -976,7 +976,7 @@ TarmacParserRecord::TarmacParserRecord(Tick _when, ThreadContext *_thread, void TarmacParserRecord::dump() { - ostream &outs = Trace::output(); + std::ostream &outs = Trace::output(); uint64_t written_data = 0; unsigned mem_flags = 3 | ArmISA::TLB::AllowUnaligned; @@ -1005,8 +1005,8 @@ TarmacParserRecord::dump() if (pc.instAddr() != instRecord.addr) { if (!mismatch) printMismatchHeader(staticInst, pc); - outs << "diff> [PC] gem5: 0x" << hex << pc.instAddr() - << ", TARMAC: 0x" << instRecord.addr << endl; + outs << "diff> [PC] gem5: 0x" << std::hex << pc.instAddr() + << ", TARMAC: 0x" << instRecord.addr << std::endl; mismatch = true; mismatchOnPcOrOpcode = true; } @@ -1014,9 +1014,9 @@ TarmacParserRecord::dump() if (arm_inst->encoding() != instRecord.opcode) { if (!mismatch) printMismatchHeader(staticInst, pc); - outs << "diff> [opcode] gem5: 0x" << hex + outs << "diff> [opcode] gem5: 0x" << std::hex << arm_inst->encoding() - << ", TARMAC: 0x" << instRecord.opcode << endl; + << ", TARMAC: 0x" << instRecord.opcode << std::endl; mismatch = true; mismatchOnPcOrOpcode = true; } @@ -1049,10 +1049,10 @@ TarmacParserRecord::dump() if (written_data != memRecord.data) { if (!mismatch) printMismatchHeader(staticInst, pc); - outs << "diff> [mem(0x" << hex << memRecord.addr + outs << "diff> [mem(0x" << std::hex << memRecord.addr << ")] gem5: 0x" << written_data << ", TARMAC: 0x" << memRecord.data - << endl; + << std::endl; } break; @@ -1083,8 +1083,8 @@ TarmacParserRecord::dump() bool TarmacParserRecord::advanceTrace() { - ifstream& trace = parent.trace; - trace >> hex; // All integer values are in hex base + std::ifstream& trace = parent.trace; + trace >> std::hex; // All integer values are in hex base if (buf[0] != 'I') { trace >> buf; @@ -1201,9 +1201,9 @@ TarmacParserRecord::advanceTrace() regRecord.index = miscRegMap[buf]; } else { // Try match with upper case name (misc. register) - string reg_name = buf; - transform(reg_name.begin(), reg_name.end(), reg_name.begin(), - ::tolower); + std::string reg_name = buf; + std::transform(reg_name.begin(), reg_name.end(), reg_name.begin(), + ::tolower); if (miscRegMap.count(reg_name.c_str())) { regRecord.type = REG_MISC; regRecord.index = miscRegMap[reg_name.c_str()]; @@ -1327,7 +1327,7 @@ TarmacParser::advanceTraceToStartPc() Addr pc; int saved_offset; - trace >> hex; // All integer values are in hex base + trace >> std::hex; // All integer values are in hex base while (true) { saved_offset = trace.tellg(); @@ -1338,7 +1338,7 @@ TarmacParser::advanceTraceToStartPc() trace >> buf >> pc; if (pc == startPc) { // Set file pointer to the beginning of this line - trace.seekg(saved_offset, ios::beg); + trace.seekg(saved_offset, std::ios::beg); return; } else { trace.ignore(TarmacParserRecord::MaxLineLength, '\n');