From: Michael Nolan <mtnolan2640@gmail.com>
Date: Sat, 16 May 2020 14:02:48 +0000 (-0400)
Subject: OP_CROP fully working
X-Git-Tag: div_pipeline~1139
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d3a46d659375856d52b887e3c7e55aded645e80d;p=soc.git

OP_CROP fully working
---

diff --git a/src/soc/cr/main_stage.py b/src/soc/cr/main_stage.py
index 8708efde..53004900 100644
--- a/src/soc/cr/main_stage.py
+++ b/src/soc/cr/main_stage.py
@@ -45,18 +45,24 @@ class CRMainStage(PipeModBase):
         comb += cr_output.eq(self.i.cr)
 
         # Generate array for cr input so bits can be selected
-        cr_arr = Array([Signal() for _ in range(32)])
+        cr_arr = Array([Signal(name=f"cr_arr_{i}") for i in range(32)])
         for i in range(32):
             comb += cr_arr[i].eq(self.i.cr[31-i])
 
         # Generate array for cr output so the bit to write to can be
         # selected by a signal
-        cr_out_arr = Array([Signal() for _ in range(32)])
+        cr_out_arr = Array([Signal(name=f"cr_out_{i}") for i in range(32)])
         for i in range(32):
             comb += cr_output[31-i].eq(cr_out_arr[i])
             comb += cr_out_arr[i].eq(cr_arr[i])
             
 
+        # Grab the lookup table for cr_op type instructions
+        lut = Signal(4, reset_less=True)
+        # There's no field, just have to grab it directly from the insn
+        comb += lut.eq(self.i.ctx.op.insn[6:10])
+            
+
         with m.Switch(op.insn_type):
             with m.Case(InternalOp.OP_MCRF):
                 bf = Signal(xl_fields['BF'][0:-1].shape())
@@ -66,6 +72,25 @@ class CRMainStage(PipeModBase):
 
                 for i in range(4):
                     comb += cr_out_arr[bf*4 + i].eq(cr_arr[bfa*4 + i])
+            with m.Case(InternalOp.OP_CROP):
+                bt = Signal(xl_fields['BT'][0:-1].shape())
+                comb += bt.eq(xl_fields['BT'][0:-1])
+                ba = Signal(xl_fields['BA'][0:-1].shape())
+                comb += ba.eq(xl_fields['BA'][0:-1])
+                bb = Signal(xl_fields['BB'][0:-1].shape())
+                comb += bb.eq(xl_fields['BB'][0:-1])
+
+                bit_a = Signal(reset_less=True)
+                bit_b = Signal(reset_less=True)
+                comb += bit_a.eq(cr_arr[ba])
+                comb += bit_b.eq(cr_arr[bb])
+
+                bit_out = Signal(reset_less=True)
+                comb += bit_out.eq(Mux(bit_b,
+                                       Mux(bit_a, lut[3], lut[1]),
+                                       Mux(bit_a, lut[2], lut[0])))
+                comb += cr_out_arr[bt].eq(bit_out)
+                
 
                 
         comb += self.o.cr.eq(cr_output)
diff --git a/src/soc/cr/test/test_pipe_caller.py b/src/soc/cr/test/test_pipe_caller.py
index 6b5e8020..1ce5b520 100644
--- a/src/soc/cr/test/test_pipe_caller.py
+++ b/src/soc/cr/test/test_pipe_caller.py
@@ -66,9 +66,18 @@ class CRTestCase(FHDLTestCase):
                       self.test_name)
         test_data.append(tc)
 
-    def test_crand(self):
-        lst = ["crandc 1, 2, 3"]
-        self.run_tst_program(Program(lst))
+    def test_crop(self):
+        insns = ["crand", "cror", "crnand", "crnor", "crxor", "creqv",
+                 "crandc", "crorc"]
+        for i in range(40):
+            choice = random.choice(insns)
+            ba = random.randint(0, 31)
+            bb = random.randint(0, 31)
+            bt = random.randint(0, 31)
+            lst = [f"{choice} {ba}, {bb}, {bt}"]
+            cr = random.randint(0, 7)
+            self.run_tst_program(Program(lst), initial_cr=cr)
+
 
     def test_mcrf(self):
         lst = ["mcrf 0, 5"]