From: Cesar Strauss <cestrauss@gmail.com>
Date: Fri, 14 Aug 2020 11:06:49 +0000 (-0300)
Subject: Demonstrates adding extra debug signals traces to the dump file
X-Git-Tag: semi_working_ecp5~335
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d3a72bb0688cf343dddc069ef50ba60b9736e8d9;p=soc.git

Demonstrates adding extra debug signals traces to the dump file

At simulation time, you can declare a new signal, and use it inside
the test case, as any other signal. By including it in the "traces"
parameter of Simulator.write_vcd, it is included in the trace dump file.

Useful for adding "printf" style debugging for GTKWave.
---

diff --git a/src/soc/experiment/alu_fsm.py b/src/soc/experiment/alu_fsm.py
index 3a3d9db1..2cdc7c32 100644
--- a/src/soc/experiment/alu_fsm.py
+++ b/src/soc/experiment/alu_fsm.py
@@ -212,6 +212,7 @@ def write_gtkw(base_name, top_dut_name, loc):
     # color styles
     style_input = GTKWColor.orange
     style_output = GTKWColor.yellow
+    style_debug = GTKWColor.red
     with open(base_name + ".gtkw", "wt") as gtkw_file:
         gtkw = GTKWSave(gtkw_file)
         gtkw.comment("Auto-generated by " + loc)
@@ -231,6 +232,11 @@ def write_gtkw(base_name, top_dut_name, loc):
                        datafmt='dec')
             gtkw.trace(dut + "p_valid_i", color=style_input)
             gtkw.trace(dut + "p_ready_o", color=style_output)
+        with gtkw.group("debug"):
+            gtkw.blank("Some debug statements")
+            # change the displayed name in the panel
+            gtkw.trace("top.zero", alias='zero delay shift',
+                       color=style_debug)
         with gtkw.group("internal"):
             gtkw.trace(dut + "fsm_state")
             gtkw.trace(dut + "count[3:0]")
@@ -260,6 +266,11 @@ def test_shifter():
     sim = Simulator(m)
     sim.add_clock(1e-6)
 
+    # demonstrates adding extra debug signal traces
+    # they end up in the top module
+    #
+    zero = Signal()  # mark an interesting place
+
     def send(data, shift, direction):
         # present input data and assert valid_i
         yield dut.p.data_i.data.eq(data)
@@ -306,12 +317,18 @@ def test_shifter():
         # 3 << 4 = 48
         yield from receive(48)
         # 21 << 0 = 21
+        # you can look for the rising edge of this signal to quickly
+        # locate this point in the traces
+        yield zero.eq(1)
         yield from receive(21)
+        yield zero.eq(0)
 
     sim.add_sync_process(producer)
     sim.add_sync_process(consumer)
     sim_writer = sim.write_vcd(
         "test_shifter.vcd",
+        # include additional signals in the trace dump
+        traces=[zero]
     )
     with sim_writer:
         sim.run()