From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 28 Feb 2019 03:43:05 +0000 (+0000)
Subject: narrowing down rounding error to use of Norm1 module
X-Git-Tag: ls180-24jan2020~1796
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d3a98f8059ea45d4093957e38e9e56f1dbfc25da;p=ieee754fpu.git

narrowing down rounding error to use of Norm1 module
---

diff --git a/src/add/nmigen_add_experiment.py b/src/add/nmigen_add_experiment.py
index 2f7b981b..53446715 100644
--- a/src/add/nmigen_add_experiment.py
+++ b/src/add/nmigen_add_experiment.py
@@ -583,7 +583,7 @@ class FPNorm2(FPState):
         self.out_of = Overflow()
 
     def action(self, m):
-        m.d.sync += self.of.copy(self.out_of)
+        #m.d.sync += self.of.copy(self.out_of)
         m.d.sync += self.z.copy(self.out_z)
         with m.If(~self.out_norm):
             m.next = "round"
@@ -793,13 +793,13 @@ class FPADD:
         m.submodules.normalise_1 = n1.mod
 
         n2 = self.add_state(FPNorm2(self.width))
-        n2.set_inputs({"z": n1.out_z, "of": of})
+        n2.set_inputs({"z": n1.out_z, "of": n1.out_of})
         n2.set_outputs({"z": z})
         n2.mod.setup(m, n1.out_z, n2.out_z, of, n2.out_of, n2.out_norm)
         m.submodules.normalise_2 = n2.mod
 
         rn = self.add_state(FPRound(self.width))
-        rn.set_inputs({"z": n2.out_z, "of": of})
+        rn.set_inputs({"z": n2.out_z, "of": n2.out_of})
         rn.set_outputs({"z": z})
         rn.mod.setup(m, n2.out_z, rn.out_z, of)
         m.submodules.roundz = rn.mod
diff --git a/src/add/test_add.py b/src/add/test_add.py
index 0d9eb858..90ef0a2a 100644
--- a/src/add/test_add.py
+++ b/src/add/test_add.py
@@ -11,6 +11,7 @@ from unit_test_single import (get_mantissa, get_exponent, get_sign, is_nan,
                                 run_edge_cases, run_corner_cases)
 
 def testbench(dut):
+    yield from check_case(dut, 0x7ed01f25, 0xff559e2c, 0xfedb1d33)
     yield from check_case(dut, 0, 0, 0)
     yield from check_case(dut, 0xFFFFFFFF, 0xC63B800A, 0x7FC00000)
     yield from check_case(dut, 0xFF800000, 0x7F800000, 0x7FC00000)
@@ -48,7 +49,6 @@ def testbench(dut):
     yield from check_case(dut, 0x51A7A358, 0x42500000, 0x51A7A358)
     yield from check_case(dut, 0x4E5693A4, 0x42500000, 0x4E5693A5)
     yield from check_case(dut, 0x42500000, 0x4E5693A4, 0x4E5693A5)
-    yield from check_case(dut, 0x7ed01f25, 0xff559e2c, 0xfedb1d33)
     #yield from check_case(dut, 1, 0, 1)
     #yield from check_case(dut, 1, 1, 1)