From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 6 Jun 2019 22:31:18 +0000 (-0700)
Subject: Fix muxcover and its techmapping
X-Git-Tag: working-ls180~1208^2~183
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d3b7ae218bd7641a40adfba7809cf0f8bdff31e6;p=yosys.git

Fix muxcover and its techmapping
---

diff --git a/techlibs/xilinx/cells_map.v b/techlibs/xilinx/cells_map.v
index 8537dc479..f0d3ebbac 100644
--- a/techlibs/xilinx/cells_map.v
+++ b/techlibs/xilinx/cells_map.v
@@ -254,11 +254,11 @@ endmodule
 module \$_MUX8_ (A, B, C, D, E, F, G, H, S, T, U, Y);
 input A, B, C, D, E, F, G, H, S, T, U;
 output Y;
-  \$__XILINX_MUX_  #(.A_SIGNED(0), .B_SIGNED(0), .A_WIDTH(8), .B_WIDTH(3), .Y_WIDTH(1)) _TECHMAP_REPLACE_ (.A({A,B,C,D,E,F,G,H}), .B({U,T,S}), .Y(Y));
+  \$__XILINX_MUX_  #(.A_SIGNED(0), .B_SIGNED(0), .A_WIDTH(8), .B_WIDTH(3), .Y_WIDTH(1)) _TECHMAP_REPLACE_ (.A({H,G,F,E,D,C,B,A}), .B({U,T,S}), .Y(Y));
 endmodule
 
 module \$_MUX16_ (A, B, C, D, E, F, G, H, I, J, K, L, M, N, O, P, S, T, U, V, Y);
 input A, B, C, D, E, F, G, H, I, J, K, L, M, N, O, P, S, T, U, V;
 output Y;
-  \$__XILINX_MUX_  #(.A_SIGNED(0), .B_SIGNED(0), .A_WIDTH(16), .B_WIDTH(3), .Y_WIDTH(1)) _TECHMAP_REPLACE_ (.A({A,B,C,D,E,F,G,H,I,J,K,L,M,N,O,P}), .B({V,U,T,S}), .Y(Y));
+  \$__XILINX_MUX_  #(.A_SIGNED(0), .B_SIGNED(0), .A_WIDTH(16), .B_WIDTH(4), .Y_WIDTH(1)) _TECHMAP_REPLACE_ (.A({P,O,N,M,L,K,J,I,H,G,F,E,D,C,B,A}), .B({V,U,T,S}), .Y(Y));
 endmodule
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index a70bb23f1..a0c2c781d 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -290,7 +290,7 @@ struct SynthXilinxPass : public ScriptPass
 
 		if (check_label("map_cells")) {
 			if (!nomux || help_mode)
-				run("muxcover", "(skip if '-nomux')");
+				run("muxcover -mux8 -mux16", "(skip if '-nomux')");
 			run("techmap -map +/techmap.v -map +/xilinx/cells_map.v -map +/xilinx/ff_map.v");
 			run("dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT "
 					"-ff FDRE_1 Q INIT -ff FDCE_1 Q INIT -ff FDPE_1 Q INIT -ff FDSE_1 Q INIT");