From: lkcl <lkcl@web>
Date: Thu, 8 Jun 2023 19:46:18 +0000 (+0100)
Subject: (no commit message)
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d3b8267654e84685de9ae90ee04fa961cca902db;p=libreriscv.git

---

diff --git a/openpower/sv/rfc/ls010/trial_addi.mdwn b/openpower/sv/rfc/ls010/trial_addi.mdwn
index 00812a817..1c0363cda 100644
--- a/openpower/sv/rfc/ls010/trial_addi.mdwn
+++ b/openpower/sv/rfc/ls010/trial_addi.mdwn
@@ -1,7 +1,9 @@
 # Example demonstration instruction modified to SVP64 (better)
 
 <!-- hide -->
-Background: <https://bugs.libre-soc.org/show_bug.cgi?id=1056#c56>
+Background:
+* <https://bugs.libre-soc.org/show_bug.cgi?id=1056#c56>
+* <https://bugs.libre-soc.org/show_bug.cgi?id=1056#c63>
 <!-- show -->
 
 The idea here is to review a modified version of a Power ISA 3