From: Dan Gisselquist <zipcpu@gmail.com>
Date: Mon, 1 Oct 2018 17:41:35 +0000 (+0200)
Subject: Add read_verilog $changed support
X-Git-Tag: yosys-0.9~116^2~23
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d3be61b9dc12f5eb084ae7b5cfaefb8fc8a04de1;p=yosys.git

Add read_verilog $changed support

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---

diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc
index aa3b982d8..71eba547c 100644
--- a/frontends/ast/simplify.cc
+++ b/frontends/ast/simplify.cc
@@ -1836,7 +1836,7 @@ skip_dynamic_range_lvalue_expansion:;
 				goto apply_newNode;
 			}
 
-			if (str == "\\$stable" || str == "\\$rose" || str == "\\$fell")
+			if (str == "\\$stable" || str == "\\$rose" || str == "\\$fell" || str == "\\$changed")
 			{
 				if (GetSize(children) != 1)
 					log_file_error(filename, linenum, "System function %s got %d arguments, expected 1.\n",
@@ -1853,6 +1853,9 @@ skip_dynamic_range_lvalue_expansion:;
 				if (str == "\\$stable")
 					newNode = new AstNode(AST_EQ, past, present);
 
+				else if (str == "\\$changed")
+					newNode = new AstNode(AST_NE, past, present);
+
 				else if (str == "\\$rose")
 					newNode = new AstNode(AST_LOGIC_AND, new AstNode(AST_LOGIC_NOT, past), present);