From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 27 Oct 2018 06:20:24 +0000 (+0100)
Subject: replace freg_t typedef with actual sv_freg_t class derived from sv_regbase_t
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d3c092bdee7200e33605885d493e98ca47b730f1;p=riscv-isa-sim.git

replace freg_t typedef with actual sv_freg_t class derived from sv_regbase_t
---

diff --git a/riscv/insns/c_fsd.h b/riscv/insns/c_fsd.h
index 3b8e040..d038d9a 100644
--- a/riscv/insns/c_fsd.h
+++ b/riscv/insns/c_fsd.h
@@ -1,4 +1,4 @@
 require_extension('C');
 require_extension('D');
 require_fp;
-MMU.store_uint64(rv_add(RVC_RS1S, insn.rvc_ld_imm()), RVC_FRS2S.v[0]);
+MMU.store_uint64(rv_add(RVC_RS1S, insn.rvc_ld_imm()), ((freg_t)RVC_FRS2S).v[0]);
diff --git a/riscv/insns/c_fsdsp.h b/riscv/insns/c_fsdsp.h
index 1a4d50c..ab3c69b 100644
--- a/riscv/insns/c_fsdsp.h
+++ b/riscv/insns/c_fsdsp.h
@@ -1,4 +1,4 @@
 require_extension('C');
 require_extension('D');
 require_fp;
-MMU.store_uint64(rv_add(RVC_SP, insn.rvc_sdsp_imm()), RVC_FRS2.v[0]);
+MMU.store_uint64(rv_add(RVC_SP, insn.rvc_sdsp_imm()), ((freg_t)RVC_FRS2).v[0]);
diff --git a/riscv/insns/c_fsw.h b/riscv/insns/c_fsw.h
index e400d72..2f03210 100644
--- a/riscv/insns/c_fsw.h
+++ b/riscv/insns/c_fsw.h
@@ -2,7 +2,7 @@ require_extension('C');
 if (xlen == 32) {
   require_extension('F');
   require_fp;
-  MMU.store_uint32(rv_add(RVC_RS1S, insn.rvc_lw_imm()), RVC_FRS2S.v[0]);
+  MMU.store_uint32(rv_add(RVC_RS1S, insn.rvc_lw_imm()), ((freg_t)RVC_FRS2S).v[0]);
 } else { // c.sd
   MMU.store_uint64(rv_add(RVC_RS1S, insn.rvc_ld_imm()), RVC_RS2S);
 }
diff --git a/riscv/insns/c_fswsp.h b/riscv/insns/c_fswsp.h
index cbf9264..fff75fc 100644
--- a/riscv/insns/c_fswsp.h
+++ b/riscv/insns/c_fswsp.h
@@ -2,7 +2,7 @@ require_extension('C');
 if (xlen == 32) {
   require_extension('F');
   require_fp;
-  MMU.store_uint32(rv_add(RVC_SP, insn.rvc_swsp_imm()), RVC_FRS2.v[0]);
+  MMU.store_uint32(rv_add(RVC_SP, insn.rvc_swsp_imm()), ((freg_t)RVC_FRS2).v[0]);
 } else { // c.sdsp
   MMU.store_uint64(rv_add(RVC_SP, insn.rvc_sdsp_imm()), RVC_RS2);
 }
diff --git a/riscv/insns/fmv_x_d.h b/riscv/insns/fmv_x_d.h
index e1a23f4..e292ed0 100644
--- a/riscv/insns/fmv_x_d.h
+++ b/riscv/insns/fmv_x_d.h
@@ -1,4 +1,4 @@
 require_extension('D');
 require_rv64;
 require_fp;
-WRITE_RD(FRS1.v[0]);
+WRITE_RD(((freg_t)FRS1).v[0]);
diff --git a/riscv/insns/fmv_x_w.h b/riscv/insns/fmv_x_w.h
index ca23310..987ce7b 100644
--- a/riscv/insns/fmv_x_w.h
+++ b/riscv/insns/fmv_x_w.h
@@ -1,3 +1,3 @@
 require_extension('F');
 require_fp;
-WRITE_RD(sext32(sv_reg_t(FRS1.v[0])));
+WRITE_RD(sext32(sv_reg_t(((freg_t)FRS1).v[0])));
diff --git a/riscv/insns/fsd.h b/riscv/insns/fsd.h
index f1a76ab..0383806 100644
--- a/riscv/insns/fsd.h
+++ b/riscv/insns/fsd.h
@@ -1,3 +1,3 @@
 require_extension('D');
 require_fp;
-MMU.store_uint64(rv_add(RS1, insn.s_imm()), FRS2.v[0]);
+MMU.store_uint64(rv_add(RS1, insn.s_imm()), ((freg_t)FRS2).v[0]);
diff --git a/riscv/insns/fsw.h b/riscv/insns/fsw.h
index 226e30e..d125246 100644
--- a/riscv/insns/fsw.h
+++ b/riscv/insns/fsw.h
@@ -1,3 +1,3 @@
 require_extension('F');
 require_fp;
-MMU.store_uint32(rv_add(RS1, insn.s_imm()), FRS2.v[0]);
+MMU.store_uint32(rv_add(RS1, insn.s_imm()), ((freg_t)FRS2).v[0]);
diff --git a/riscv/sv_insn_redirect.cc b/riscv/sv_insn_redirect.cc
index 5c5d628..e93ace4 100644
--- a/riscv/sv_insn_redirect.cc
+++ b/riscv/sv_insn_redirect.cc
@@ -17,7 +17,7 @@ void (sv_proc_t::WRITE_FRD)(sv_float64_t value)
 
 void (sv_proc_t::WRITE_FRD)(sv_freg_t value)
 {
-    fprintf(stderr, "WRITE_FRD fsv_reg_t %lx\n", value.v[0]);
+    fprintf(stderr, "WRITE_FRD fsv_reg_t %lx\n", ((freg_t)value).v[0]);
     DO_WRITE_FREG( _insn->rd(), freg(value) );
 }
 
diff --git a/riscv/sv_insn_redirect.h b/riscv/sv_insn_redirect.h
index 90f2791..56cf9a8 100644
--- a/riscv/sv_insn_redirect.h
+++ b/riscv/sv_insn_redirect.h
@@ -59,7 +59,7 @@ class insn_t;
 typedef float32_t sv_float32_t;
 typedef float64_t sv_float64_t;
 typedef float128_t sv_float128_t;
-typedef freg_t sv_freg_t;
+//typedef freg_t sv_freg_t;
 
 class sv_proc_t
 {
diff --git a/riscv/sv_reg.h b/riscv/sv_reg.h
index 8bdc940..b6f003e 100644
--- a/riscv/sv_reg.h
+++ b/riscv/sv_reg.h
@@ -75,4 +75,20 @@ public:
 inline sv_reg_t::operator sv_sreg_t() const &
 { return sv_sreg_t((int64_t)reg, elwidth); }
 
+class sv_freg_t : public sv_regbase_t {
+public:
+    sv_freg_t(freg_t _reg) : sv_regbase_t(), reg(_reg) { } // default elwidth
+    sv_freg_t(freg_t _reg, uint8_t _elwidth) :
+                sv_regbase_t(_elwidth), reg(_reg)
+                                                {}
+    sv_freg_t(freg_t _reg, int xlen, uint8_t _elwidth) :
+                sv_regbase_t(xlen, _elwidth), reg(_reg)
+                                                {}
+
+    freg_t reg;
+public:
+
+  operator freg_t() const& { return reg; }
+};
+
 #endif