From: Chad Versace <chad.versace@intel.com>
Date: Thu, 7 Apr 2011 16:09:38 +0000 (-0700)
Subject: i965: Change assertion condition from implicit to explicit
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d3cc3901ab67823af3aba08efc863daa22ed1408;p=mesa.git

i965: Change assertion condition from implicit to explicit

... because grokking explicit assertions requires fewer neurons.

In brw_misc_state.c:emit_depthbuffer, change assertion condition
    tiling != I915_TILING_X && tiling != I915_TILING_NONE
to
    tiling == I915_TILING_Y

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Chad Versace <chad.versace@intel.com>
---

diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c b/src/mesa/drivers/dri/i965/brw_misc_state.c
index 74e911b4ddb..19eea07ebc6 100644
--- a/src/mesa/drivers/dri/i965/brw_misc_state.c
+++ b/src/mesa/drivers/dri/i965/brw_misc_state.c
@@ -248,8 +248,7 @@ static void emit_depthbuffer(struct brw_context *brw)
       }
 
       assert(region->tiling != I915_TILING_X);
-      if (intel->gen >= 6)
-	 assert(region->tiling != I915_TILING_NONE);
+      assert(intel->gen < 6 || region->tiling == I915_TILING_Y);
 
       BEGIN_BATCH(len);
       OUT_BATCH(_3DSTATE_DEPTH_BUFFER << 16 | (len - 2));