From: Gabe Black Date: Thu, 7 Mar 2019 11:02:35 +0000 (-0800) Subject: arch, cpu, dev, gpu, mem, sim, python: start using getPort. X-Git-Tag: v19.0.0.0~1035 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d3d24835bcc03ecf312ac6ba7df114656770730f;p=gem5.git arch, cpu, dev, gpu, mem, sim, python: start using getPort. Replace the getMasterPort, getSlavePort, and getEthPort functions with getPort, and remove extraneous mechanisms that are no longer necessary. Change-Id: Iab7e3c02d2f3a0cf33e7e824e18c28646b5bc318 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17040 Reviewed-by: Daniel Carvalho Reviewed-by: Andreas Sandberg Maintainer: Andreas Sandberg --- diff --git a/src/arch/arm/table_walker.cc b/src/arch/arm/table_walker.cc index 1a7b5d375..21257de59 100644 --- a/src/arch/arm/table_walker.cc +++ b/src/arch/arm/table_walker.cc @@ -114,8 +114,8 @@ TableWalker::init() fatal_if(!tlb, "Table walker must have a valid TLB\n"); } -BaseMasterPort& -TableWalker::getMasterPort(const std::string &if_name, PortID idx) +Port & +TableWalker::getPort(const std::string &if_name, PortID idx) { if (if_name == "port") { if (!isStage2) { @@ -124,7 +124,7 @@ TableWalker::getMasterPort(const std::string &if_name, PortID idx) fatal("Cannot access table walker port through stage-two walker\n"); } } - return MemObject::getMasterPort(if_name, idx); + return MemObject::getPort(if_name, idx); } TableWalker::WalkerState::WalkerState() : diff --git a/src/arch/arm/table_walker.hh b/src/arch/arm/table_walker.hh index 57e3aed06..8176fc7f5 100644 --- a/src/arch/arm/table_walker.hh +++ b/src/arch/arm/table_walker.hh @@ -889,8 +889,8 @@ class TableWalker : public MemObject DrainState drain() override; void drainResume() override; - BaseMasterPort& getMasterPort(const std::string &if_name, - PortID idx = InvalidPortID) override; + Port &getPort(const std::string &if_name, + PortID idx=InvalidPortID) override; void regStats() override; diff --git a/src/arch/arm/tlb.cc b/src/arch/arm/tlb.cc index ed7e68039..dc3c35bab 100644 --- a/src/arch/arm/tlb.cc +++ b/src/arch/arm/tlb.cc @@ -1243,8 +1243,8 @@ TLB::translateComplete(const RequestPtr &req, ThreadContext *tc, return fault; } -BaseMasterPort* -TLB::getTableWalkerMasterPort() +Port * +TLB::getTableWalkerPort() { return &stage2Mmu->getPort(); } diff --git a/src/arch/arm/tlb.hh b/src/arch/arm/tlb.hh index 8ca176a82..fa1b04069 100644 --- a/src/arch/arm/tlb.hh +++ b/src/arch/arm/tlb.hh @@ -392,7 +392,7 @@ class TLB : public BaseTLB void regProbePoints() override; /** - * Get the table walker master port. This is used for migrating + * Get the table walker port. This is used for migrating * port connections during a CPU takeOverFrom() call. For * architectures that do not have a table walker, NULL is * returned, hence the use of a pointer rather than a @@ -401,7 +401,7 @@ class TLB : public BaseTLB * * @return A pointer to the walker master port */ - BaseMasterPort* getTableWalkerMasterPort() override; + Port *getTableWalkerPort() override; // Caching misc register values here. // Writing to misc registers needs to invalidate them. diff --git a/src/arch/generic/tlb.hh b/src/arch/generic/tlb.hh index 7865d8abe..ba07b1057 100644 --- a/src/arch/generic/tlb.hh +++ b/src/arch/generic/tlb.hh @@ -131,15 +131,15 @@ class BaseTLB : public MemObject virtual void takeOverFrom(BaseTLB *otlb) = 0; /** - * Get the table walker master port if present. This is used for + * Get the table walker port if present. This is used for * migrating port connections during a CPU takeOverFrom() * call. For architectures that do not have a table walker, NULL * is returned, hence the use of a pointer rather than a * reference. * - * @return A pointer to the walker master port or NULL if not present + * @return A pointer to the walker port or NULL if not present */ - virtual BaseMasterPort* getTableWalkerMasterPort() { return NULL; } + virtual Port* getTableWalkerPort() { return NULL; } void memInvalidate() { flushAll(); } }; diff --git a/src/arch/x86/interrupts.hh b/src/arch/x86/interrupts.hh index bfd188961..dfdff2b3f 100644 --- a/src/arch/x86/interrupts.hh +++ b/src/arch/x86/interrupts.hh @@ -215,22 +215,15 @@ class Interrupts : public BasicPioDevice, IntDevice AddrRangeList getIntAddrRange() const override; - BaseMasterPort &getMasterPort(const std::string &if_name, - PortID idx = InvalidPortID) override + Port &getPort(const std::string &if_name, + PortID idx=InvalidPortID) override { if (if_name == "int_master") { return intMasterPort; - } - return BasicPioDevice::getMasterPort(if_name, idx); - } - - BaseSlavePort &getSlavePort(const std::string &if_name, - PortID idx = InvalidPortID) override - { - if (if_name == "int_slave") { + } else if (if_name == "int_slave") { return intSlavePort; } - return BasicPioDevice::getSlavePort(if_name, idx); + return BasicPioDevice::getPort(if_name, idx); } /* diff --git a/src/arch/x86/pagetable_walker.cc b/src/arch/x86/pagetable_walker.cc index 4a405f25f..0741dc2ed 100644 --- a/src/arch/x86/pagetable_walker.cc +++ b/src/arch/x86/pagetable_walker.cc @@ -167,13 +167,13 @@ bool Walker::sendTiming(WalkerState* sendingState, PacketPtr pkt) } -BaseMasterPort & -Walker::getMasterPort(const std::string &if_name, PortID idx) +Port & +Walker::getPort(const std::string &if_name, PortID idx) { if (if_name == "port") return port; else - return MemObject::getMasterPort(if_name, idx); + return MemObject::getPort(if_name, idx); } void diff --git a/src/arch/x86/pagetable_walker.hh b/src/arch/x86/pagetable_walker.hh index edca24795..c1f4ed2c4 100644 --- a/src/arch/x86/pagetable_walker.hh +++ b/src/arch/x86/pagetable_walker.hh @@ -160,8 +160,8 @@ namespace X86ISA const RequestPtr &req, BaseTLB::Mode mode); Fault startFunctional(ThreadContext * _tc, Addr &addr, unsigned &logBytes, BaseTLB::Mode mode); - BaseMasterPort &getMasterPort(const std::string &if_name, - PortID idx = InvalidPortID); + Port &getPort(const std::string &if_name, + PortID idx=InvalidPortID) override; protected: // The TLB we're supposed to load. diff --git a/src/arch/x86/tlb.cc b/src/arch/x86/tlb.cc index 59fd3f00a..33de0583e 100644 --- a/src/arch/x86/tlb.cc +++ b/src/arch/x86/tlb.cc @@ -511,10 +511,10 @@ TLB::unserialize(CheckpointIn &cp) } } -BaseMasterPort * -TLB::getTableWalkerMasterPort() +Port * +TLB::getTableWalkerPort() { - return &walker->getMasterPort("port"); + return &walker->getPort("port"); } } // namespace X86ISA diff --git a/src/arch/x86/tlb.hh b/src/arch/x86/tlb.hh index 8894a1e4a..b969bca9d 100644 --- a/src/arch/x86/tlb.hh +++ b/src/arch/x86/tlb.hh @@ -156,16 +156,16 @@ namespace X86ISA void unserialize(CheckpointIn &cp) override; /** - * Get the table walker master port. This is used for + * Get the table walker port. This is used for * migrating port connections during a CPU takeOverFrom() * call. For architectures that do not have a table walker, * NULL is returned, hence the use of a pointer rather than a * reference. For X86 this method will always return a valid * port pointer. * - * @return A pointer to the walker master port + * @return A pointer to the walker port */ - BaseMasterPort *getTableWalkerMasterPort() override; + Port *getTableWalkerPort() override; }; } diff --git a/src/cpu/base.cc b/src/cpu/base.cc index 09de64646..8dfcf3cda 100644 --- a/src/cpu/base.cc +++ b/src/cpu/base.cc @@ -449,19 +449,18 @@ BaseCPU::regStats() threadContexts[0]->regStats(name()); } -BaseMasterPort & -BaseCPU::getMasterPort(const string &if_name, PortID idx) +Port & +BaseCPU::getPort(const string &if_name, PortID idx) { // Get the right port based on name. This applies to all the // subclasses of the base CPU and relies on their implementation - // of getDataPort and getInstPort. In all cases there methods - // return a MasterPort pointer. + // of getDataPort and getInstPort. if (if_name == "dcache_port") return getDataPort(); else if (if_name == "icache_port") return getInstPort(); else - return MemObject::getMasterPort(if_name, idx); + return MemObject::getPort(if_name, idx); } void @@ -621,21 +620,18 @@ BaseCPU::takeOverFrom(BaseCPU *oldCPU) ThreadContext::compare(oldTC, newTC); */ - BaseMasterPort *old_itb_port = - oldTC->getITBPtr()->getTableWalkerMasterPort(); - BaseMasterPort *old_dtb_port = - oldTC->getDTBPtr()->getTableWalkerMasterPort(); - BaseMasterPort *new_itb_port = - newTC->getITBPtr()->getTableWalkerMasterPort(); - BaseMasterPort *new_dtb_port = - newTC->getDTBPtr()->getTableWalkerMasterPort(); + Port *old_itb_port = oldTC->getITBPtr()->getTableWalkerPort(); + Port *old_dtb_port = oldTC->getDTBPtr()->getTableWalkerPort(); + Port *new_itb_port = newTC->getITBPtr()->getTableWalkerPort(); + Port *new_dtb_port = newTC->getDTBPtr()->getTableWalkerPort(); // Move over any table walker ports if they exist if (new_itb_port) { assert(!new_itb_port->isConnected()); assert(old_itb_port); assert(old_itb_port->isConnected()); - BaseSlavePort &slavePort = old_itb_port->getSlavePort(); + auto &slavePort = + dynamic_cast(old_itb_port)->getSlavePort(); old_itb_port->unbind(); new_itb_port->bind(slavePort); } @@ -643,7 +639,8 @@ BaseCPU::takeOverFrom(BaseCPU *oldCPU) assert(!new_dtb_port->isConnected()); assert(old_dtb_port); assert(old_dtb_port->isConnected()); - BaseSlavePort &slavePort = old_dtb_port->getSlavePort(); + auto &slavePort = + dynamic_cast(old_dtb_port)->getSlavePort(); old_dtb_port->unbind(); new_dtb_port->bind(slavePort); } @@ -655,14 +652,14 @@ BaseCPU::takeOverFrom(BaseCPU *oldCPU) CheckerCPU *oldChecker = oldTC->getCheckerCpuPtr(); CheckerCPU *newChecker = newTC->getCheckerCpuPtr(); if (oldChecker && newChecker) { - BaseMasterPort *old_checker_itb_port = - oldChecker->getITBPtr()->getTableWalkerMasterPort(); - BaseMasterPort *old_checker_dtb_port = - oldChecker->getDTBPtr()->getTableWalkerMasterPort(); - BaseMasterPort *new_checker_itb_port = - newChecker->getITBPtr()->getTableWalkerMasterPort(); - BaseMasterPort *new_checker_dtb_port = - newChecker->getDTBPtr()->getTableWalkerMasterPort(); + Port *old_checker_itb_port = + oldChecker->getITBPtr()->getTableWalkerPort(); + Port *old_checker_dtb_port = + oldChecker->getDTBPtr()->getTableWalkerPort(); + Port *new_checker_itb_port = + newChecker->getITBPtr()->getTableWalkerPort(); + Port *new_checker_dtb_port = + newChecker->getDTBPtr()->getTableWalkerPort(); newChecker->getITBPtr()->takeOverFrom(oldChecker->getITBPtr()); newChecker->getDTBPtr()->takeOverFrom(oldChecker->getDTBPtr()); @@ -672,8 +669,9 @@ BaseCPU::takeOverFrom(BaseCPU *oldCPU) assert(!new_checker_itb_port->isConnected()); assert(old_checker_itb_port); assert(old_checker_itb_port->isConnected()); - BaseSlavePort &slavePort = - old_checker_itb_port->getSlavePort(); + auto &slavePort = + dynamic_cast(old_checker_itb_port)-> + getSlavePort(); old_checker_itb_port->unbind(); new_checker_itb_port->bind(slavePort); } @@ -681,8 +679,9 @@ BaseCPU::takeOverFrom(BaseCPU *oldCPU) assert(!new_checker_dtb_port->isConnected()); assert(old_checker_dtb_port); assert(old_checker_dtb_port->isConnected()); - BaseSlavePort &slavePort = - old_checker_dtb_port->getSlavePort(); + auto &slavePort = + dynamic_cast(old_checker_dtb_port)-> + getSlavePort(); old_checker_dtb_port->unbind(); new_checker_dtb_port->bind(slavePort); } @@ -709,13 +708,15 @@ BaseCPU::takeOverFrom(BaseCPU *oldCPU) // we are switching to. assert(!getInstPort().isConnected()); assert(oldCPU->getInstPort().isConnected()); - BaseSlavePort &inst_peer_port = oldCPU->getInstPort().getSlavePort(); + auto &inst_peer_port = + dynamic_cast(oldCPU->getInstPort()).getSlavePort(); oldCPU->getInstPort().unbind(); getInstPort().bind(inst_peer_port); assert(!getDataPort().isConnected()); assert(oldCPU->getDataPort().isConnected()); - BaseSlavePort &data_peer_port = oldCPU->getDataPort().getSlavePort(); + auto &data_peer_port = + dynamic_cast(oldCPU->getDataPort()).getSlavePort(); oldCPU->getDataPort().unbind(); getDataPort().bind(data_peer_port); } diff --git a/src/cpu/base.hh b/src/cpu/base.hh index 8673d2330..9075d4b33 100644 --- a/src/cpu/base.hh +++ b/src/cpu/base.hh @@ -180,7 +180,7 @@ class BaseCPU : public MemObject MasterID instMasterId() { return _instMasterId; } /** - * Get a master port on this CPU. All CPUs have a data and + * Get a port on this CPU. All CPUs have a data and * instruction port, and this method uses getDataPort and * getInstPort of the subclasses to resolve the two ports. * @@ -189,8 +189,8 @@ class BaseCPU : public MemObject * * @return a reference to the port with the given name */ - BaseMasterPort &getMasterPort(const std::string &if_name, - PortID idx = InvalidPortID) override; + Port &getPort(const std::string &if_name, + PortID idx=InvalidPortID) override; /** Get cpu task id */ uint32_t taskId() const { return _taskId; } diff --git a/src/cpu/testers/directedtest/RubyDirectedTester.cc b/src/cpu/testers/directedtest/RubyDirectedTester.cc index be7f3c256..cd367b498 100644 --- a/src/cpu/testers/directedtest/RubyDirectedTester.cc +++ b/src/cpu/testers/directedtest/RubyDirectedTester.cc @@ -78,15 +78,15 @@ RubyDirectedTester::init() generator->setDirectedTester(this); } -BaseMasterPort & -RubyDirectedTester::getMasterPort(const std::string &if_name, PortID idx) +Port & +RubyDirectedTester::getPort(const std::string &if_name, PortID idx) { if (if_name != "cpuPort") { // pass it along to our super class - return MemObject::getMasterPort(if_name, idx); + return MemObject::getPort(if_name, idx); } else { if (idx >= static_cast(ports.size())) { - panic("RubyDirectedTester::getMasterPort: unknown index %d\n", idx); + panic("RubyDirectedTester::getPort: unknown index %d\n", idx); } return *ports[idx]; diff --git a/src/cpu/testers/directedtest/RubyDirectedTester.hh b/src/cpu/testers/directedtest/RubyDirectedTester.hh index 00278a65e..0f519762c 100644 --- a/src/cpu/testers/directedtest/RubyDirectedTester.hh +++ b/src/cpu/testers/directedtest/RubyDirectedTester.hh @@ -67,8 +67,8 @@ class RubyDirectedTester : public MemObject RubyDirectedTester(const Params *p); ~RubyDirectedTester(); - virtual BaseMasterPort &getMasterPort(const std::string &if_name, - PortID idx = InvalidPortID); + Port &getPort(const std::string &if_name, + PortID idx=InvalidPortID) override; MasterPort* getCpuPort(int idx); diff --git a/src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.cc b/src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.cc index 0ced9df84..1a07205e6 100644 --- a/src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.cc +++ b/src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.cc @@ -110,13 +110,13 @@ GarnetSyntheticTraffic::GarnetSyntheticTraffic(const Params *p) name(), id); } -BaseMasterPort & -GarnetSyntheticTraffic::getMasterPort(const std::string &if_name, PortID idx) +Port & +GarnetSyntheticTraffic::getPort(const std::string &if_name, PortID idx) { if (if_name == "test") return cachePort; else - return MemObject::getMasterPort(if_name, idx); + return MemObject::getPort(if_name, idx); } void diff --git a/src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.hh b/src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.hh index 3da7e2774..a18f5bbda 100644 --- a/src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.hh +++ b/src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.hh @@ -64,8 +64,8 @@ class GarnetSyntheticTraffic : public MemObject // main simulation loop (one cycle) void tick(); - virtual BaseMasterPort &getMasterPort(const std::string &if_name, - PortID idx = InvalidPortID); + Port &getPort(const std::string &if_name, + PortID idx=InvalidPortID) override; /** * Print state of address in memory system via PrintReq (for diff --git a/src/cpu/testers/memtest/memtest.cc b/src/cpu/testers/memtest/memtest.cc index 09e7e88a1..346f88246 100644 --- a/src/cpu/testers/memtest/memtest.cc +++ b/src/cpu/testers/memtest/memtest.cc @@ -124,13 +124,13 @@ MemTest::MemTest(const Params *p) schedule(noResponseEvent, clockEdge(progressCheck)); } -BaseMasterPort & -MemTest::getMasterPort(const std::string &if_name, PortID idx) +Port & +MemTest::getPort(const std::string &if_name, PortID idx) { if (if_name == "port") return port; else - return MemObject::getMasterPort(if_name, idx); + return MemObject::getPort(if_name, idx); } void diff --git a/src/cpu/testers/memtest/memtest.hh b/src/cpu/testers/memtest/memtest.hh index 023b878c9..8e8f73996 100644 --- a/src/cpu/testers/memtest/memtest.hh +++ b/src/cpu/testers/memtest/memtest.hh @@ -77,8 +77,8 @@ class MemTest : public MemObject virtual void regStats(); - virtual BaseMasterPort &getMasterPort(const std::string &if_name, - PortID idx = InvalidPortID); + Port &getPort(const std::string &if_name, + PortID idx=InvalidPortID) override; protected: diff --git a/src/cpu/testers/rubytest/RubyTester.cc b/src/cpu/testers/rubytest/RubyTester.cc index 93754467d..cb23688c4 100644 --- a/src/cpu/testers/rubytest/RubyTester.cc +++ b/src/cpu/testers/rubytest/RubyTester.cc @@ -128,17 +128,17 @@ RubyTester::init() m_checkTable_ptr = new CheckTable(m_num_writers, m_num_readers, this); } -BaseMasterPort & -RubyTester::getMasterPort(const std::string &if_name, PortID idx) +Port & +RubyTester::getPort(const std::string &if_name, PortID idx) { if (if_name != "cpuInstPort" && if_name != "cpuInstDataPort" && if_name != "cpuDataPort") { // pass it along to our super class - return MemObject::getMasterPort(if_name, idx); + return MemObject::getPort(if_name, idx); } else { if (if_name == "cpuInstPort") { if (idx > m_num_inst_only_ports) { - panic("RubyTester::getMasterPort: unknown inst port %d\n", + panic("RubyTester::getPort: unknown inst port %d\n", idx); } // @@ -147,7 +147,7 @@ RubyTester::getMasterPort(const std::string &if_name, PortID idx) return *readPorts[idx]; } else if (if_name == "cpuInstDataPort") { if (idx > m_num_inst_data_ports) { - panic("RubyTester::getMasterPort: unknown inst+data port %d\n", + panic("RubyTester::getPort: unknown inst+data port %d\n", idx); } int read_idx = idx + m_num_inst_only_ports; @@ -162,7 +162,7 @@ RubyTester::getMasterPort(const std::string &if_name, PortID idx) // if (idx > (static_cast(readPorts.size()) - (m_num_inst_only_ports + m_num_inst_data_ports))) { - panic("RubyTester::getMasterPort: unknown data port %d\n", + panic("RubyTester::getPort: unknown data port %d\n", idx); } int read_idx = idx + m_num_inst_only_ports + m_num_inst_data_ports; diff --git a/src/cpu/testers/rubytest/RubyTester.hh b/src/cpu/testers/rubytest/RubyTester.hh index 007035977..2509aa2cd 100644 --- a/src/cpu/testers/rubytest/RubyTester.hh +++ b/src/cpu/testers/rubytest/RubyTester.hh @@ -94,8 +94,8 @@ class RubyTester : public MemObject RubyTester(const Params *p); ~RubyTester(); - virtual BaseMasterPort &getMasterPort(const std::string &if_name, - PortID idx = InvalidPortID); + Port &getPort(const std::string &if_name, + PortID idx=InvalidPortID) override; bool isInstOnlyCpuPort(int idx); bool isInstDataCpuPort(int idx); diff --git a/src/cpu/testers/traffic_gen/base.cc b/src/cpu/testers/traffic_gen/base.cc index ad4f67d9d..80fa8a9d6 100644 --- a/src/cpu/testers/traffic_gen/base.cc +++ b/src/cpu/testers/traffic_gen/base.cc @@ -88,13 +88,13 @@ BaseTrafficGen::~BaseTrafficGen() { } -BaseMasterPort& -BaseTrafficGen::getMasterPort(const string& if_name, PortID idx) +Port & +BaseTrafficGen::getPort(const string &if_name, PortID idx) { if (if_name == "port") { return port; } else { - return MemObject::getMasterPort(if_name, idx); + return MemObject::getPort(if_name, idx); } } diff --git a/src/cpu/testers/traffic_gen/base.hh b/src/cpu/testers/traffic_gen/base.hh index 272dcb587..2443e6223 100644 --- a/src/cpu/testers/traffic_gen/base.hh +++ b/src/cpu/testers/traffic_gen/base.hh @@ -182,8 +182,8 @@ class BaseTrafficGen : public MemObject ~BaseTrafficGen(); - BaseMasterPort& getMasterPort(const std::string &if_name, - PortID idx = InvalidPortID) override; + Port &getPort(const std::string &if_name, + PortID idx=InvalidPortID) override; void init() override; diff --git a/src/cpu/trace/trace_cpu.cc b/src/cpu/trace/trace_cpu.cc index 2b198e966..6e499dbac 100644 --- a/src/cpu/trace/trace_cpu.cc +++ b/src/cpu/trace/trace_cpu.cc @@ -108,13 +108,13 @@ TraceCPU::takeOverFrom(BaseCPU *oldCPU) // Unbind the ports of the old CPU and bind the ports of the TraceCPU. assert(!getInstPort().isConnected()); assert(oldCPU->getInstPort().isConnected()); - BaseSlavePort &inst_peer_port = oldCPU->getInstPort().getSlavePort(); + Port &inst_peer_port = oldCPU->getInstPort().getSlavePort(); oldCPU->getInstPort().unbind(); getInstPort().bind(inst_peer_port); assert(!getDataPort().isConnected()); assert(oldCPU->getDataPort().isConnected()); - BaseSlavePort &data_peer_port = oldCPU->getDataPort().getSlavePort(); + Port &data_peer_port = oldCPU->getDataPort().getSlavePort(); oldCPU->getDataPort().unbind(); getDataPort().bind(data_peer_port); } diff --git a/src/dev/dma_device.cc b/src/dev/dma_device.cc index c445fbc77..047eef1d7 100644 --- a/src/dev/dma_device.cc +++ b/src/dev/dma_device.cc @@ -262,13 +262,13 @@ DmaPort::sendDma() panic("Unknown memory mode."); } -BaseMasterPort & -DmaDevice::getMasterPort(const std::string &if_name, PortID idx) +Port & +DmaDevice::getPort(const std::string &if_name, PortID idx) { if (if_name == "dma") { return dmaPort; } - return PioDevice::getMasterPort(if_name, idx); + return PioDevice::getPort(if_name, idx); } diff --git a/src/dev/dma_device.hh b/src/dev/dma_device.hh index 0dc79df42..f556e14e3 100644 --- a/src/dev/dma_device.hh +++ b/src/dev/dma_device.hh @@ -179,8 +179,8 @@ class DmaDevice : public PioDevice unsigned int cacheBlockSize() const { return sys->cacheLineSize(); } - BaseMasterPort &getMasterPort(const std::string &if_name, - PortID idx = InvalidPortID) override; + Port &getPort(const std::string &if_name, + PortID idx=InvalidPortID) override; }; diff --git a/src/dev/io_device.cc b/src/dev/io_device.cc index 28ea52aad..1cec2bf4a 100644 --- a/src/dev/io_device.cc +++ b/src/dev/io_device.cc @@ -87,13 +87,13 @@ PioDevice::init() pioPort.sendRangeChange(); } -BaseSlavePort & -PioDevice::getSlavePort(const std::string &if_name, PortID idx) +Port & +PioDevice::getPort(const std::string &if_name, PortID idx) { if (if_name == "pio") { return pioPort; } - return MemObject::getSlavePort(if_name, idx); + return MemObject::getPort(if_name, idx); } BasicPioDevice::BasicPioDevice(const Params *p, Addr size) diff --git a/src/dev/io_device.hh b/src/dev/io_device.hh index 7e323b3bc..64d7aa5ec 100644 --- a/src/dev/io_device.hh +++ b/src/dev/io_device.hh @@ -125,8 +125,8 @@ class PioDevice : public MemObject virtual void init(); - virtual BaseSlavePort &getSlavePort(const std::string &if_name, - PortID idx = InvalidPortID); + Port &getPort(const std::string &if_name, + PortID idx=InvalidPortID) override; friend class PioPort; diff --git a/src/dev/net/Ethernet.py b/src/dev/net/Ethernet.py index 0cf37e230..7ef83744c 100644 --- a/src/dev/net/Ethernet.py +++ b/src/dev/net/Ethernet.py @@ -47,7 +47,6 @@ from m5.objects.PciDevice import PciDevice class EtherLink(SimObject): type = 'EtherLink' cxx_header = "dev/net/etherlink.hh" - cxx_extra_bases = [ "EtherObject" ] int0 = SlavePort("interface 0") int1 = SlavePort("interface 1") delay = Param.Latency('0us', "packet transmit delay") @@ -58,7 +57,6 @@ class EtherLink(SimObject): class DistEtherLink(SimObject): type = 'DistEtherLink' cxx_header = "dev/net/dist_etherlink.hh" - cxx_extra_bases = [ "EtherObject" ] int0 = SlavePort("interface 0") delay = Param.Latency('0us', "packet transmit delay") delay_var = Param.Latency('0ns', "packet transmit delay variability") @@ -77,7 +75,6 @@ class DistEtherLink(SimObject): class EtherBus(SimObject): type = 'EtherBus' cxx_header = "dev/net/etherbus.hh" - cxx_extra_bases = [ "EtherObject" ] loopback = Param.Bool(True, "send packet back to the sending interface") dump = Param.EtherDump(NULL, "dump object") speed = Param.NetworkBandwidth('100Mbps', "bus speed in bits per second") @@ -85,7 +82,6 @@ class EtherBus(SimObject): class EtherSwitch(SimObject): type = 'EtherSwitch' cxx_header = "dev/net/etherswitch.hh" - cxx_extra_bases = [ "EtherObject" ] dump = Param.EtherDump(NULL, "dump object") fabric_speed = Param.NetworkBandwidth('10Gbps', "switch fabric speed in bits " "per second") @@ -99,7 +95,6 @@ class EtherTapBase(SimObject): type = 'EtherTapBase' abstract = True cxx_header = "dev/net/ethertap.hh" - cxx_extra_bases = [ "EtherObject" ] bufsz = Param.Int(10000, "tap buffer size") dump = Param.EtherDump(NULL, "dump object") tap = SlavePort("Ethernet interface to connect to gem5's network") @@ -127,7 +122,6 @@ class EtherDevice(PciDevice): type = 'EtherDevice' abstract = True cxx_header = "dev/net/etherdevice.hh" - cxx_extra_bases = [ "EtherObject" ] interface = MasterPort("Ethernet Interface") class IGbE(EtherDevice): diff --git a/src/dev/net/SConscript b/src/dev/net/SConscript index 0bb6bbf01..908dd44e6 100644 --- a/src/dev/net/SConscript +++ b/src/dev/net/SConscript @@ -45,7 +45,6 @@ Import('*') SimObject('Ethernet.py') -Source('python.cc', add_tags='python') # Basic Ethernet infrastructure Source('etherbus.cc') diff --git a/src/dev/net/dist_etherlink.cc b/src/dev/net/dist_etherlink.cc index 477ad61b3..0cefb90fd 100644 --- a/src/dev/net/dist_etherlink.cc +++ b/src/dev/net/dist_etherlink.cc @@ -61,7 +61,6 @@ #include "dev/net/etherdump.hh" #include "dev/net/etherint.hh" #include "dev/net/etherlink.hh" -#include "dev/net/etherobject.hh" #include "dev/net/etherpkt.hh" #include "dev/net/tcp_iface.hh" #include "params/EtherLink.hh" @@ -109,15 +108,12 @@ DistEtherLink::~DistEtherLink() delete distIface; } -EtherInt* -DistEtherLink::getEthPort(const std::string &if_name, int idx) +Port & +DistEtherLink::getPort(const std::string &if_name, PortID idx) { - if (if_name != "int0") { - return nullptr; - } else { - panic_if(localIface->getPeer(), "interface already connected to"); - } - return localIface; + if (if_name == "int0") + return *localIface; + return SimObject::getPort(if_name, idx); } void diff --git a/src/dev/net/dist_etherlink.hh b/src/dev/net/dist_etherlink.hh index 51852a519..7d00602c9 100644 --- a/src/dev/net/dist_etherlink.hh +++ b/src/dev/net/dist_etherlink.hh @@ -53,7 +53,6 @@ #include #include "dev/net/etherlink.hh" -#include "dev/net/etherobject.hh" #include "params/DistEtherLink.hh" class DistIface; @@ -62,7 +61,7 @@ class EthPacketData; /** * Model for a fixed bandwidth full duplex ethernet link. */ -class DistEtherLink : public SimObject, public EtherObject +class DistEtherLink : public SimObject { protected: class LocalIface; @@ -224,7 +223,8 @@ class DistEtherLink : public SimObject, public EtherObject return dynamic_cast(_params); } - EtherInt *getEthPort(const std::string &if_name, int idx) override; + Port &getPort(const std::string &if_name, + PortID idx=InvalidPortID) override; virtual void init() override; virtual void startup() override; diff --git a/src/dev/net/etherbus.cc b/src/dev/net/etherbus.cc index dee772cc0..fa49b9900 100644 --- a/src/dev/net/etherbus.cc +++ b/src/dev/net/etherbus.cc @@ -81,8 +81,8 @@ EtherBus::txDone() packet = 0; } -EtherInt* -EtherBus::getEthPort(const std::string &if_name, int idx) +Port & +EtherBus::getPort(const std::string &if_name, PortID idx) { panic("Etherbus doesn't work\n"); } diff --git a/src/dev/net/etherbus.hh b/src/dev/net/etherbus.hh index 8c1260fc5..24333b53d 100644 --- a/src/dev/net/etherbus.hh +++ b/src/dev/net/etherbus.hh @@ -35,7 +35,6 @@ #ifndef __DEV_NET_ETHERBUS_HH__ #define __DEV_NET_ETHERBUS_HH__ -#include "dev/net/etherobject.hh" #include "dev/net/etherpkt.hh" #include "params/EtherBus.hh" #include "sim/eventq.hh" @@ -43,7 +42,7 @@ class EtherDump; class EtherInt; -class EtherBus : public SimObject, public EtherObject +class EtherBus : public SimObject { protected: typedef std::list devlist_t; @@ -72,7 +71,8 @@ class EtherBus : public SimObject, public EtherObject void reg(EtherInt *dev); bool busy() const { return (bool)packet; } bool send(EtherInt *sender, EthPacketPtr &packet); - EtherInt *getEthPort(const std::string &if_name, int idx) override; + Port &getPort(const std::string &if_name, + PortID idx=InvalidPortID) override; }; #endif // __DEV_NET_ETHERBUS_HH__ diff --git a/src/dev/net/etherdevice.hh b/src/dev/net/etherdevice.hh index 7101ec80a..7de4d82a4 100644 --- a/src/dev/net/etherdevice.hh +++ b/src/dev/net/etherdevice.hh @@ -37,7 +37,6 @@ #define __DEV_NET_ETHERDEVICE_HH__ #include "base/statistics.hh" -#include "dev/net/etherobject.hh" #include "dev/pci/device.hh" #include "params/EtherDevBase.hh" #include "params/EtherDevice.hh" @@ -45,7 +44,7 @@ class EtherInt; -class EtherDevice : public PciDevice, public EtherObject +class EtherDevice : public PciDevice { public: typedef EtherDeviceParams Params; diff --git a/src/dev/net/etherlink.cc b/src/dev/net/etherlink.cc index b160e29d5..448bb8856 100644 --- a/src/dev/net/etherlink.cc +++ b/src/dev/net/etherlink.cc @@ -88,20 +88,14 @@ EtherLink::~EtherLink() delete interface[1]; } -EtherInt* -EtherLink::getEthPort(const std::string &if_name, int idx) +Port & +EtherLink::getPort(const std::string &if_name, PortID idx) { - Interface *i; if (if_name == "int0") - i = interface[0]; + return *interface[0]; else if (if_name == "int1") - i = interface[1]; - else - return NULL; - if (i->getPeer()) - panic("interface already connected to\n"); - - return i; + return *interface[1]; + return SimObject::getPort(if_name, idx); } diff --git a/src/dev/net/etherlink.hh b/src/dev/net/etherlink.hh index 37fa16859..9f12ca461 100644 --- a/src/dev/net/etherlink.hh +++ b/src/dev/net/etherlink.hh @@ -51,7 +51,6 @@ #include "base/types.hh" #include "dev/net/etherint.hh" -#include "dev/net/etherobject.hh" #include "dev/net/etherpkt.hh" #include "params/EtherLink.hh" #include "sim/eventq.hh" @@ -62,7 +61,7 @@ class Checkpoint; /* * Model for a fixed bandwidth full duplex ethernet link */ -class EtherLink : public EtherObject, public SimObject +class EtherLink : public SimObject { protected: class Interface; @@ -152,7 +151,8 @@ class EtherLink : public EtherObject, public SimObject return dynamic_cast(_params); } - EtherInt *getEthPort(const std::string &if_name, int idx) override; + Port &getPort(const std::string &if_name, + PortID idx=InvalidPortID) override; void serialize(CheckpointOut &cp) const override; void unserialize(CheckpointIn &cp) override; diff --git a/src/dev/net/etherobject.hh b/src/dev/net/etherobject.hh deleted file mode 100644 index 638c50667..000000000 --- a/src/dev/net/etherobject.hh +++ /dev/null @@ -1,54 +0,0 @@ -/* - * Copyright (c) 2007 The Regents of The University of Michigan - * Copyright 2019 Google, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Ali Saidi - * Gabe Black - */ - -/** - * @file - * Base Ethernet Object declaration. - */ - -#ifndef __DEV_NET_ETHEROBJECT_HH__ -#define __DEV_NET_ETHEROBJECT_HH__ - -#include - -class EtherInt; - -/** - * The base EtherObject interface. - */ -class EtherObject -{ - public: - virtual EtherInt *getEthPort(const std::string &if_name, int idx=-1) = 0; -}; - -#endif // __DEV_NET_ETHEROBJECT_HH__ diff --git a/src/dev/net/etherswitch.cc b/src/dev/net/etherswitch.cc index c03b59435..99e0621a2 100644 --- a/src/dev/net/etherswitch.cc +++ b/src/dev/net/etherswitch.cc @@ -62,16 +62,15 @@ EtherSwitch::~EtherSwitch() interfaces.clear(); } -EtherInt* -EtherSwitch::getEthPort(const std::string &if_name, int idx) +Port & +EtherSwitch::getPort(const std::string &if_name, PortID idx) { - if (idx < 0 || idx >= interfaces.size()) - return nullptr; - - Interface *interface = interfaces.at(idx); - panic_if(interface->getPeer(), "interface already connected\n"); + if (if_name == "interface") { + panic_if(idx < 0 || idx >= interfaces.size(), "index out of bounds"); + return *interfaces.at(idx); + } - return interface; + return SimObject::getPort(if_name, idx); } bool diff --git a/src/dev/net/etherswitch.hh b/src/dev/net/etherswitch.hh index 36a0c686a..9b60b8507 100644 --- a/src/dev/net/etherswitch.hh +++ b/src/dev/net/etherswitch.hh @@ -42,14 +42,13 @@ #include "base/inet.hh" #include "dev/net/etherint.hh" #include "dev/net/etherlink.hh" -#include "dev/net/etherobject.hh" #include "dev/net/etherpkt.hh" #include "dev/net/pktfifo.hh" #include "params/EtherSwitch.hh" #include "sim/eventq.hh" #include "sim/sim_object.hh" -class EtherSwitch : public SimObject, public EtherObject +class EtherSwitch : public SimObject { public: typedef EtherSwitchParams Params; @@ -62,7 +61,8 @@ class EtherSwitch : public SimObject, public EtherObject return dynamic_cast(_params); } - EtherInt *getEthPort(const std::string &if_name, int idx) override; + Port &getPort(const std::string &if_name, + PortID idx=InvalidPortID) override; protected: /** diff --git a/src/dev/net/ethertap.cc b/src/dev/net/ethertap.cc index bf2dc6885..552296d5c 100644 --- a/src/dev/net/ethertap.cc +++ b/src/dev/net/ethertap.cc @@ -159,15 +159,12 @@ EtherTapBase::stopPolling() } -EtherInt* -EtherTapBase::getEthPort(const std::string &if_name, int idx) +Port & +EtherTapBase::getPort(const std::string &if_name, PortID idx) { - if (if_name == "tap") { - if (interface->getPeer()) - panic("Interface already connected to\n"); - return interface; - } - return NULL; + if (if_name == "tap") + return *interface; + return SimObject::getPort(if_name, idx); } bool diff --git a/src/dev/net/ethertap.hh b/src/dev/net/ethertap.hh index 7db73c5b4..5f59a390c 100644 --- a/src/dev/net/ethertap.hh +++ b/src/dev/net/ethertap.hh @@ -41,7 +41,6 @@ #include "base/pollevent.hh" #include "config/use_tuntap.hh" #include "dev/net/etherint.hh" -#include "dev/net/etherobject.hh" #include "dev/net/etherpkt.hh" #if USE_TUNTAP @@ -56,7 +55,7 @@ class TapEvent; class EtherTapInt; -class EtherTapBase : public SimObject, public EtherObject +class EtherTapBase : public SimObject { public: typedef EtherTapBaseParams Params; @@ -101,7 +100,8 @@ class EtherTapBase : public SimObject, public EtherObject EtherTapInt *interface; public: - EtherInt *getEthPort(const std::string &if_name, int idx) override; + Port &getPort(const std::string &if_name, + PortID idx=InvalidPortID) override; bool recvSimulated(EthPacketPtr packet); void sendSimulated(void *data, size_t len); diff --git a/src/dev/net/i8254xGBe.cc b/src/dev/net/i8254xGBe.cc index 2d55603f1..9d83519df 100644 --- a/src/dev/net/i8254xGBe.cc +++ b/src/dev/net/i8254xGBe.cc @@ -139,16 +139,12 @@ IGbE::init() PciDevice::init(); } -EtherInt* -IGbE::getEthPort(const std::string &if_name, int idx) +Port & +IGbE::getPort(const std::string &if_name, PortID idx) { - - if (if_name == "interface") { - if (etherInt->getPeer()) - panic("Port already connected to\n"); - return etherInt; - } - return NULL; + if (if_name == "interface") + return *etherInt; + return EtherDevice::getPort(if_name, idx); } Tick diff --git a/src/dev/net/i8254xGBe.hh b/src/dev/net/i8254xGBe.hh index 402e61d95..031cb4d91 100644 --- a/src/dev/net/i8254xGBe.hh +++ b/src/dev/net/i8254xGBe.hh @@ -519,7 +519,8 @@ class IGbE : public EtherDevice ~IGbE(); void init() override; - EtherInt *getEthPort(const std::string &if_name, int idx) override; + Port &getPort(const std::string &if_name, + PortID idx=InvalidPortID) override; Tick lastInterrupt; diff --git a/src/dev/net/ns_gige.cc b/src/dev/net/ns_gige.cc index 1a5adb275..29e886717 100644 --- a/src/dev/net/ns_gige.cc +++ b/src/dev/net/ns_gige.cc @@ -173,15 +173,12 @@ NSGigE::writeConfig(PacketPtr pkt) return configDelay; } -EtherInt* -NSGigE::getEthPort(const std::string &if_name, int idx) +Port & +NSGigE::getPort(const std::string &if_name, PortID idx) { - if (if_name == "interface") { - if (interface->getPeer()) - panic("interface already connected to\n"); - return interface; - } - return NULL; + if (if_name == "interface") + return *interface; + return EtherDevBase::getPort(if_name, idx); } /** diff --git a/src/dev/net/ns_gige.hh b/src/dev/net/ns_gige.hh index f9be02890..5745c3040 100644 --- a/src/dev/net/ns_gige.hh +++ b/src/dev/net/ns_gige.hh @@ -341,7 +341,8 @@ class NSGigE : public EtherDevBase NSGigE(Params *params); ~NSGigE(); - EtherInt *getEthPort(const std::string &if_name, int idx) override; + Port &getPort(const std::string &if_name, + PortID idx=InvalidPortID) override; Tick writeConfig(PacketPtr pkt) override; diff --git a/src/dev/net/python.cc b/src/dev/net/python.cc deleted file mode 100644 index a012074c1..000000000 --- a/src/dev/net/python.cc +++ /dev/null @@ -1,48 +0,0 @@ -/* - * Copyright 2019 Google, Inc. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Gabe Black - */ - -#include "python/pybind11/pybind.hh" - -#include "dev/net/etherobject.hh" -#include "sim/init.hh" - -namespace -{ - -void -ethernet_pybind(pybind11::module &m_internal) -{ - pybind11::module m = m_internal.def_submodule("ethernet"); - pybind11::class_< - EtherObject, std::unique_ptr>( - m, "EtherObject"); -} -EmbeddedPyBind embed_("ethernet", ðernet_pybind); - -} // anonymous namespace diff --git a/src/dev/net/sinic.cc b/src/dev/net/sinic.cc index ce9fbb6a3..8d73d1542 100644 --- a/src/dev/net/sinic.cc +++ b/src/dev/net/sinic.cc @@ -142,16 +142,12 @@ Device::resetStats() _maxVnicDistance = 0; } -EtherInt* -Device::getEthPort(const std::string &if_name, int idx) +Port & +Device::getPort(const std::string &if_name, PortID idx) { - if (if_name == "interface") { - if (interface->getPeer()) - panic("interface already connected to\n"); - - return interface; - } - return NULL; + if (if_name == "interface") + return *interface; + return EtherDevBase::getPort(if_name, idx); } diff --git a/src/dev/net/sinic.hh b/src/dev/net/sinic.hh index 70d22f12d..ab79a5f6f 100644 --- a/src/dev/net/sinic.hh +++ b/src/dev/net/sinic.hh @@ -230,7 +230,8 @@ class Device : public Base public: bool recvPacket(EthPacketPtr packet); void transferDone(); - EtherInt *getEthPort(const std::string &if_name, int idx) override; + Port &getPort(const std::string &if_name, + PortID idx=InvalidPortID) override; /** * DMA parameters diff --git a/src/dev/pci/copy_engine.cc b/src/dev/pci/copy_engine.cc index 7f8959aca..2a74c5c0c 100644 --- a/src/dev/pci/copy_engine.cc +++ b/src/dev/pci/copy_engine.cc @@ -113,24 +113,24 @@ CopyEngine::CopyEngineChannel::~CopyEngineChannel() delete [] copyBuffer; } -BaseMasterPort & -CopyEngine::getMasterPort(const std::string &if_name, PortID idx) +Port & +CopyEngine::getPort(const std::string &if_name, PortID idx) { if (if_name != "dma") { // pass it along to our super class - return PciDevice::getMasterPort(if_name, idx); + return PciDevice::getPort(if_name, idx); } else { if (idx >= static_cast(chan.size())) { - panic("CopyEngine::getMasterPort: unknown index %d\n", idx); + panic("CopyEngine::getPort: unknown index %d\n", idx); } - return chan[idx]->getMasterPort(); + return chan[idx]->getPort(); } } -BaseMasterPort & -CopyEngine::CopyEngineChannel::getMasterPort() +Port & +CopyEngine::CopyEngineChannel::getPort() { return cePort; } diff --git a/src/dev/pci/copy_engine.hh b/src/dev/pci/copy_engine.hh index 1ec29f02e..eb62fd3b7 100644 --- a/src/dev/pci/copy_engine.hh +++ b/src/dev/pci/copy_engine.hh @@ -95,7 +95,7 @@ class CopyEngine : public PciDevice public: CopyEngineChannel(CopyEngine *_ce, int cid); virtual ~CopyEngineChannel(); - BaseMasterPort &getMasterPort(); + Port &getPort(); std::string name() { assert(ce); return ce->name() + csprintf("-chan%d", channelId); } virtual Tick read(PacketPtr pkt) @@ -193,8 +193,8 @@ class CopyEngine : public PciDevice void regStats() override; - BaseMasterPort &getMasterPort(const std::string &if_name, - PortID idx = InvalidPortID) override; + Port &getPort(const std::string &if_name, + PortID idx = InvalidPortID) override; Tick read(PacketPtr pkt) override; Tick write(PacketPtr pkt) override; diff --git a/src/dev/x86/i82094aa.cc b/src/dev/x86/i82094aa.cc index 2b09f14a5..fccc98469 100644 --- a/src/dev/x86/i82094aa.cc +++ b/src/dev/x86/i82094aa.cc @@ -70,12 +70,12 @@ X86ISA::I82094AA::init() IntDevice::init(); } -BaseMasterPort & -X86ISA::I82094AA::getMasterPort(const std::string &if_name, PortID idx) +Port & +X86ISA::I82094AA::getPort(const std::string &if_name, PortID idx) { if (if_name == "int_master") return intMasterPort; - return BasicPioDevice::getMasterPort(if_name, idx); + return BasicPioDevice::getPort(if_name, idx); } AddrRangeList diff --git a/src/dev/x86/i82094aa.hh b/src/dev/x86/i82094aa.hh index c9e2f1c81..d5cb42f79 100644 --- a/src/dev/x86/i82094aa.hh +++ b/src/dev/x86/i82094aa.hh @@ -102,8 +102,8 @@ class I82094AA : public BasicPioDevice, public IntDevice void writeReg(uint8_t offset, uint32_t value); uint32_t readReg(uint8_t offset); - BaseMasterPort &getMasterPort(const std::string &if_name, - PortID idx = InvalidPortID) override; + Port &getPort(const std::string &if_name, + PortID idx=InvalidPortID) override; Tick recvResponse(PacketPtr pkt) override; diff --git a/src/gpu-compute/compute_unit.hh b/src/gpu-compute/compute_unit.hh index c15e7e0f3..cfe25d7d8 100644 --- a/src/gpu-compute/compute_unit.hh +++ b/src/gpu-compute/compute_unit.hh @@ -691,8 +691,8 @@ class ComputeUnit : public MemObject // port to the SQC TLB (there's a separate TLB for each I-cache) ITLBPort *sqcTLBPort; - virtual BaseMasterPort& - getMasterPort(const std::string &if_name, PortID idx) + Port & + getPort(const std::string &if_name, PortID idx) override { if (if_name == "memory_port") { memPort[idx] = new DataPort(csprintf("%s-port%d", name(), idx), diff --git a/src/gpu-compute/dispatcher.cc b/src/gpu-compute/dispatcher.cc index db250c28b..211e399d2 100644 --- a/src/gpu-compute/dispatcher.cc +++ b/src/gpu-compute/dispatcher.cc @@ -251,14 +251,14 @@ GpuDispatcher::write(PacketPtr pkt) } -BaseMasterPort& -GpuDispatcher::getMasterPort(const std::string &if_name, PortID idx) +Port & +GpuDispatcher::getPort(const std::string &if_name, PortID idx) { if (if_name == "translation_port") { return *tlbPort; } - return DmaDevice::getMasterPort(if_name, idx); + return DmaDevice::getPort(if_name, idx); } void diff --git a/src/gpu-compute/dispatcher.hh b/src/gpu-compute/dispatcher.hh index 92956e2d5..17dc5a5cc 100644 --- a/src/gpu-compute/dispatcher.hh +++ b/src/gpu-compute/dispatcher.hh @@ -140,8 +140,8 @@ class GpuDispatcher : public DmaDevice TLBPort *tlbPort; - virtual BaseMasterPort& getMasterPort(const std::string &if_name, - PortID idx); + Port &getPort(const std::string &if_name, + PortID idx=InvalidPortID) override; AddrRangeList getAddrRanges() const; Tick read(PacketPtr pkt); diff --git a/src/gpu-compute/gpu_tlb.cc b/src/gpu-compute/gpu_tlb.cc index 9e07b0547..c23b9986f 100644 --- a/src/gpu-compute/gpu_tlb.cc +++ b/src/gpu-compute/gpu_tlb.cc @@ -137,33 +137,25 @@ namespace X86ISA assert(translationReturnEvent.empty()); } - BaseSlavePort& - GpuTLB::getSlavePort(const std::string &if_name, PortID idx) + Port & + GpuTLB::getPort(const std::string &if_name, PortID idx) { if (if_name == "slave") { if (idx >= static_cast(cpuSidePort.size())) { - panic("TLBCoalescer::getSlavePort: unknown index %d\n", idx); + panic("TLBCoalescer::getPort: unknown index %d\n", idx); } return *cpuSidePort[idx]; - } else { - panic("TLBCoalescer::getSlavePort: unknown port %s\n", if_name); - } - } - - BaseMasterPort& - GpuTLB::getMasterPort(const std::string &if_name, PortID idx) - { - if (if_name == "master") { + } else if (if_name == "master") { if (idx >= static_cast(memSidePort.size())) { - panic("TLBCoalescer::getMasterPort: unknown index %d\n", idx); + panic("TLBCoalescer::getPort: unknown index %d\n", idx); } hasMemSidePort = true; return *memSidePort[idx]; } else { - panic("TLBCoalescer::getMasterPort: unknown port %s\n", if_name); + panic("TLBCoalescer::getPort: unknown port %s\n", if_name); } } diff --git a/src/gpu-compute/gpu_tlb.hh b/src/gpu-compute/gpu_tlb.hh index 9ca478d91..80510d7a0 100644 --- a/src/gpu-compute/gpu_tlb.hh +++ b/src/gpu-compute/gpu_tlb.hh @@ -308,11 +308,8 @@ namespace X86ISA // TLB ports on the memory side std::vector memSidePort; - BaseMasterPort &getMasterPort(const std::string &if_name, - PortID idx=InvalidPortID); - - BaseSlavePort &getSlavePort(const std::string &if_name, - PortID idx=InvalidPortID); + Port &getPort(const std::string &if_name, + PortID idx=InvalidPortID) override; /** * TLB TranslationState: this currently is a somewhat bastardization of diff --git a/src/gpu-compute/lds_state.hh b/src/gpu-compute/lds_state.hh index ccf758b47..05bc11ed6 100644 --- a/src/gpu-compute/lds_state.hh +++ b/src/gpu-compute/lds_state.hh @@ -436,8 +436,8 @@ class LdsState: public MemObject return range; } - virtual BaseSlavePort & - getSlavePort(const std::string& if_name, PortID idx) + Port & + getPort(const std::string &if_name, PortID idx) { if (if_name == "cuPort") { // TODO need to set name dynamically at this point? diff --git a/src/gpu-compute/tlb_coalescer.cc b/src/gpu-compute/tlb_coalescer.cc index 193c44ed8..3b7631a74 100644 --- a/src/gpu-compute/tlb_coalescer.cc +++ b/src/gpu-compute/tlb_coalescer.cc @@ -67,31 +67,23 @@ TLBCoalescer::TLBCoalescer(const Params *p) } } -BaseSlavePort& -TLBCoalescer::getSlavePort(const std::string &if_name, PortID idx) +Port & +TLBCoalescer::getPort(const std::string &if_name, PortID idx) { if (if_name == "slave") { if (idx >= static_cast(cpuSidePort.size())) { - panic("TLBCoalescer::getSlavePort: unknown index %d\n", idx); + panic("TLBCoalescer::getPort: unknown index %d\n", idx); } return *cpuSidePort[idx]; - } else { - panic("TLBCoalescer::getSlavePort: unknown port %s\n", if_name); - } -} - -BaseMasterPort& -TLBCoalescer::getMasterPort(const std::string &if_name, PortID idx) -{ - if (if_name == "master") { + } else if (if_name == "master") { if (idx >= static_cast(memSidePort.size())) { - panic("TLBCoalescer::getMasterPort: unknown index %d\n", idx); + panic("TLBCoalescer::getPort: unknown index %d\n", idx); } return *memSidePort[idx]; } else { - panic("TLBCoalescer::getMasterPort: unknown port %s\n", if_name); + panic("TLBCoalescer::getPort: unknown port %s\n", if_name); } } diff --git a/src/gpu-compute/tlb_coalescer.hh b/src/gpu-compute/tlb_coalescer.hh index 0294e4ff4..2aff81027 100644 --- a/src/gpu-compute/tlb_coalescer.hh +++ b/src/gpu-compute/tlb_coalescer.hh @@ -211,8 +211,8 @@ class TLBCoalescer : public MemObject // Coalescer master ports on the memory side std::vector memSidePort; - BaseMasterPort& getMasterPort(const std::string &if_name, PortID idx); - BaseSlavePort& getSlavePort(const std::string &if_name, PortID idx); + Port &getPort(const std::string &if_name, + PortID idx=InvalidPortID) override; void processProbeTLBEvent(); /// This event issues the TLB probes diff --git a/src/learning_gem5/part2/simple_cache.cc b/src/learning_gem5/part2/simple_cache.cc index 1ddb5155e..880dc39ad 100644 --- a/src/learning_gem5/part2/simple_cache.cc +++ b/src/learning_gem5/part2/simple_cache.cc @@ -51,30 +51,20 @@ SimpleCache::SimpleCache(SimpleCacheParams *params) : } } -BaseMasterPort& -SimpleCache::getMasterPort(const std::string& if_name, PortID idx) +Port & +SimpleCache::getPort(const std::string &if_name, PortID idx) { panic_if(idx != InvalidPortID, "This object doesn't support vector ports"); // This is the name from the Python SimObject declaration in SimpleCache.py if (if_name == "mem_side") { return memPort; - } else { - // pass it along to our super class - return MemObject::getMasterPort(if_name, idx); - } -} - -BaseSlavePort& -SimpleCache::getSlavePort(const std::string& if_name, PortID idx) -{ - // This is the name from the Python SimObject declaration (SimpleMemobj.py) - if (if_name == "cpu_side" && idx < cpuPorts.size()) { + } else if (if_name == "cpu_side" && idx < cpuPorts.size()) { // We should have already created all of the ports in the constructor return cpuPorts[idx]; } else { // pass it along to our super class - return MemObject::getSlavePort(if_name, idx); + return MemObject::getPort(if_name, idx); } } diff --git a/src/learning_gem5/part2/simple_cache.hh b/src/learning_gem5/part2/simple_cache.hh index 7d53ffed0..56859eb77 100644 --- a/src/learning_gem5/part2/simple_cache.hh +++ b/src/learning_gem5/part2/simple_cache.hh @@ -304,30 +304,17 @@ class SimpleCache : public MemObject SimpleCache(SimpleCacheParams *params); /** - * Get a master port with a given name and index. This is used at + * Get a port with a given name and index. This is used at * binding time and returns a reference to a protocol-agnostic - * base master port. + * port. * * @param if_name Port name * @param idx Index in the case of a VectorPort * * @return A reference to the given port */ - virtual BaseMasterPort& getMasterPort(const std::string& if_name, - PortID idx = InvalidPortID) override; - - /** - * Get a slave port with a given name and index. This is used at - * binding time and returns a reference to a protocol-agnostic - * base master port. - * - * @param if_name Port name - * @param idx Index in the case of a VectorPort - * - * @return A reference to the given port - */ - virtual BaseSlavePort& getSlavePort(const std::string& if_name, - PortID idx = InvalidPortID) override; + Port &getPort(const std::string &if_name, + PortID idx=InvalidPortID) override; /** * Register the stats diff --git a/src/learning_gem5/part2/simple_memobj.cc b/src/learning_gem5/part2/simple_memobj.cc index cb4d3d8db..c9af3461f 100644 --- a/src/learning_gem5/part2/simple_memobj.cc +++ b/src/learning_gem5/part2/simple_memobj.cc @@ -41,33 +41,21 @@ SimpleMemobj::SimpleMemobj(SimpleMemobjParams *params) : { } -BaseMasterPort& -SimpleMemobj::getMasterPort(const std::string& if_name, PortID idx) +Port & +SimpleMemobj::getPort(const std::string &if_name, PortID idx) { panic_if(idx != InvalidPortID, "This object doesn't support vector ports"); // This is the name from the Python SimObject declaration (SimpleMemobj.py) if (if_name == "mem_side") { return memPort; - } else { - // pass it along to our super class - return MemObject::getMasterPort(if_name, idx); - } -} - -BaseSlavePort& -SimpleMemobj::getSlavePort(const std::string& if_name, PortID idx) -{ - panic_if(idx != InvalidPortID, "This object doesn't support vector ports"); - - // This is the name from the Python SimObject declaration in SimpleCache.py - if (if_name == "inst_port") { + } else if (if_name == "inst_port") { return instPort; } else if (if_name == "data_port") { return dataPort; } else { // pass it along to our super class - return MemObject::getSlavePort(if_name, idx); + return MemObject::getPort(if_name, idx); } } diff --git a/src/learning_gem5/part2/simple_memobj.hh b/src/learning_gem5/part2/simple_memobj.hh index a44d4336c..7a9b44764 100644 --- a/src/learning_gem5/part2/simple_memobj.hh +++ b/src/learning_gem5/part2/simple_memobj.hh @@ -235,30 +235,17 @@ class SimpleMemobj : public MemObject SimpleMemobj(SimpleMemobjParams *params); /** - * Get a master port with a given name and index. This is used at + * Get a port with a given name and index. This is used at * binding time and returns a reference to a protocol-agnostic - * base master port. + * port. * * @param if_name Port name * @param idx Index in the case of a VectorPort * * @return A reference to the given port */ - BaseMasterPort& getMasterPort(const std::string& if_name, - PortID idx = InvalidPortID) override; - - /** - * Get a slave port with a given name and index. This is used at - * binding time and returns a reference to a protocol-agnostic - * base master port. - * - * @param if_name Port name - * @param idx Index in the case of a VectorPort - * - * @return A reference to the given port - */ - BaseSlavePort& getSlavePort(const std::string& if_name, - PortID idx = InvalidPortID) override; + Port &getPort(const std::string &if_name, + PortID idx=InvalidPortID) override; }; diff --git a/src/mem/addr_mapper.cc b/src/mem/addr_mapper.cc index 546dd6906..958a8ad4c 100644 --- a/src/mem/addr_mapper.cc +++ b/src/mem/addr_mapper.cc @@ -53,23 +53,15 @@ AddrMapper::init() fatal("Address mapper is not connected on both sides.\n"); } -BaseMasterPort& -AddrMapper::getMasterPort(const std::string& if_name, PortID idx) +Port & +AddrMapper::getPort(const std::string &if_name, PortID idx) { if (if_name == "master") { return masterPort; - } else { - return MemObject::getMasterPort(if_name, idx); - } -} - -BaseSlavePort& -AddrMapper::getSlavePort(const std::string& if_name, PortID idx) -{ - if (if_name == "slave") { + } else if (if_name == "slave") { return slavePort; } else { - return MemObject::getSlavePort(if_name, idx); + return MemObject::getPort(if_name, idx); } } diff --git a/src/mem/addr_mapper.hh b/src/mem/addr_mapper.hh index 6765638e9..6b47cfcb8 100644 --- a/src/mem/addr_mapper.hh +++ b/src/mem/addr_mapper.hh @@ -62,11 +62,8 @@ class AddrMapper : public MemObject virtual ~AddrMapper() { } - virtual BaseMasterPort& getMasterPort(const std::string& if_name, - PortID idx = InvalidPortID); - - virtual BaseSlavePort& getSlavePort(const std::string& if_name, - PortID idx = InvalidPortID); + Port &getPort(const std::string &if_name, + PortID idx=InvalidPortID) override; virtual void init(); diff --git a/src/mem/bridge.cc b/src/mem/bridge.cc index 1066f47a0..7428e7f77 100644 --- a/src/mem/bridge.cc +++ b/src/mem/bridge.cc @@ -85,24 +85,16 @@ Bridge::Bridge(Params *p) { } -BaseMasterPort& -Bridge::getMasterPort(const std::string &if_name, PortID idx) +Port & +Bridge::getPort(const std::string &if_name, PortID idx) { if (if_name == "master") return masterPort; - else - // pass it along to our super class - return MemObject::getMasterPort(if_name, idx); -} - -BaseSlavePort& -Bridge::getSlavePort(const std::string &if_name, PortID idx) -{ - if (if_name == "slave") + else if (if_name == "slave") return slavePort; else // pass it along to our super class - return MemObject::getSlavePort(if_name, idx); + return MemObject::getPort(if_name, idx); } void diff --git a/src/mem/bridge.hh b/src/mem/bridge.hh index bb7727717..906640355 100644 --- a/src/mem/bridge.hh +++ b/src/mem/bridge.hh @@ -316,10 +316,8 @@ class Bridge : public MemObject public: - virtual BaseMasterPort& getMasterPort(const std::string& if_name, - PortID idx = InvalidPortID); - virtual BaseSlavePort& getSlavePort(const std::string& if_name, - PortID idx = InvalidPortID); + Port &getPort(const std::string &if_name, + PortID idx=InvalidPortID) override; virtual void init(); diff --git a/src/mem/cache/base.cc b/src/mem/cache/base.cc index 50622d776..19655a57e 100644 --- a/src/mem/cache/base.cc +++ b/src/mem/cache/base.cc @@ -185,23 +185,15 @@ BaseCache::init() forwardSnoops = cpuSidePort.isSnooping(); } -BaseMasterPort & -BaseCache::getMasterPort(const std::string &if_name, PortID idx) +Port & +BaseCache::getPort(const std::string &if_name, PortID idx) { if (if_name == "mem_side") { return memSidePort; - } else { - return MemObject::getMasterPort(if_name, idx); - } -} - -BaseSlavePort & -BaseCache::getSlavePort(const std::string &if_name, PortID idx) -{ - if (if_name == "cpu_side") { + } else if (if_name == "cpu_side") { return cpuSidePort; - } else { - return MemObject::getSlavePort(if_name, idx); + } else { + return MemObject::getPort(if_name, idx); } } diff --git a/src/mem/cache/base.hh b/src/mem/cache/base.hh index a7b25ff2f..a45dcba6f 100644 --- a/src/mem/cache/base.hh +++ b/src/mem/cache/base.hh @@ -1028,10 +1028,8 @@ class BaseCache : public MemObject void init() override; - BaseMasterPort &getMasterPort(const std::string &if_name, - PortID idx = InvalidPortID) override; - BaseSlavePort &getSlavePort(const std::string &if_name, - PortID idx = InvalidPortID) override; + Port &getPort(const std::string &if_name, + PortID idx=InvalidPortID) override; /** * Query block size of a cache. diff --git a/src/mem/comm_monitor.cc b/src/mem/comm_monitor.cc index 223d1cc9f..f27027dfd 100644 --- a/src/mem/comm_monitor.cc +++ b/src/mem/comm_monitor.cc @@ -83,23 +83,15 @@ CommMonitor::regProbePoints() ppPktResp.reset(new ProbePoints::Packet(getProbeManager(), "PktResponse")); } -BaseMasterPort& -CommMonitor::getMasterPort(const std::string& if_name, PortID idx) +Port & +CommMonitor::getPort(const std::string &if_name, PortID idx) { if (if_name == "master") { return masterPort; - } else { - return MemObject::getMasterPort(if_name, idx); - } -} - -BaseSlavePort& -CommMonitor::getSlavePort(const std::string& if_name, PortID idx) -{ - if (if_name == "slave") { + } else if (if_name == "slave") { return slavePort; } else { - return MemObject::getSlavePort(if_name, idx); + return MemObject::getPort(if_name, idx); } } diff --git a/src/mem/comm_monitor.hh b/src/mem/comm_monitor.hh index dac71185c..1eea6a535 100644 --- a/src/mem/comm_monitor.hh +++ b/src/mem/comm_monitor.hh @@ -84,11 +84,8 @@ class CommMonitor : public MemObject void regProbePoints() override; public: // MemObject interfaces - BaseMasterPort& getMasterPort(const std::string& if_name, - PortID idx = InvalidPortID) override; - - BaseSlavePort& getSlavePort(const std::string& if_name, - PortID idx = InvalidPortID) override; + Port &getPort(const std::string &if_name, + PortID idx=InvalidPortID) override; private: diff --git a/src/mem/dram_ctrl.cc b/src/mem/dram_ctrl.cc index b6ec4653d..dd03cf113 100644 --- a/src/mem/dram_ctrl.cc +++ b/src/mem/dram_ctrl.cc @@ -2845,11 +2845,11 @@ DRAMCtrl::recvFunctional(PacketPtr pkt) functionalAccess(pkt); } -BaseSlavePort& -DRAMCtrl::getSlavePort(const string &if_name, PortID idx) +Port & +DRAMCtrl::getPort(const string &if_name, PortID idx) { if (if_name != "port") { - return MemObject::getSlavePort(if_name, idx); + return MemObject::getPort(if_name, idx); } else { return port; } diff --git a/src/mem/dram_ctrl.hh b/src/mem/dram_ctrl.hh index a5f2fbe3e..d09223b4b 100644 --- a/src/mem/dram_ctrl.hh +++ b/src/mem/dram_ctrl.hh @@ -1176,8 +1176,8 @@ class DRAMCtrl : public QoS::MemCtrl DrainState drain() override; - virtual BaseSlavePort& getSlavePort(const std::string& if_name, - PortID idx = InvalidPortID) override; + Port &getPort(const std::string &if_name, + PortID idx=InvalidPortID) override; virtual void init() override; virtual void startup() override; diff --git a/src/mem/dramsim2.cc b/src/mem/dramsim2.cc index 6fe854364..f0c612120 100644 --- a/src/mem/dramsim2.cc +++ b/src/mem/dramsim2.cc @@ -336,11 +336,11 @@ void DRAMSim2::writeComplete(unsigned id, uint64_t addr, uint64_t cycle) signalDrainDone(); } -BaseSlavePort& -DRAMSim2::getSlavePort(const std::string &if_name, PortID idx) +Port & +DRAMSim2::getPort(const std::string &if_name, PortID idx) { if (if_name != "port") { - return MemObject::getSlavePort(if_name, idx); + return MemObject::getPort(if_name, idx); } else { return port; } diff --git a/src/mem/dramsim2.hh b/src/mem/dramsim2.hh index 6444f75d6..2fd140bb4 100644 --- a/src/mem/dramsim2.hh +++ b/src/mem/dramsim2.hh @@ -191,8 +191,8 @@ class DRAMSim2 : public AbstractMemory DrainState drain() override; - virtual BaseSlavePort& getSlavePort(const std::string& if_name, - PortID idx = InvalidPortID) override; + Port &getPort(const std::string &if_name, + PortID idx=InvalidPortID) override; void init() override; void startup() override; diff --git a/src/mem/external_master.cc b/src/mem/external_master.cc index 373aa84fe..799f85036 100644 --- a/src/mem/external_master.cc +++ b/src/mem/external_master.cc @@ -60,9 +60,8 @@ ExternalMaster::ExternalMaster(ExternalMasterParams *params) : masterId(params->system->getMasterId(this)) {} -BaseMasterPort & -ExternalMaster::getMasterPort(const std::string &if_name, - PortID idx) +Port & +ExternalMaster::getPort(const std::string &if_name, PortID idx) { if (if_name == "port") { DPRINTF(ExternalPort, "Trying to bind external port: %s %s\n", @@ -84,7 +83,7 @@ ExternalMaster::getMasterPort(const std::string &if_name, } return *externalPort; } else { - return MemObject::getMasterPort(if_name, idx); + return MemObject::getPort(if_name, idx); } } diff --git a/src/mem/external_master.hh b/src/mem/external_master.hh index d27cb4df1..42ac67c03 100644 --- a/src/mem/external_master.hh +++ b/src/mem/external_master.hh @@ -67,18 +67,18 @@ class ExternalMaster : public MemObject { public: /** Derive from this class to create an external port interface */ - class Port : public MasterPort + class ExternalPort : public MasterPort { protected: ExternalMaster &owner; public: - Port(const std::string &name_, + ExternalPort(const std::string &name_, ExternalMaster &owner_) : MasterPort(name_, &owner_), owner(owner_) { } - ~Port() { } + ~ExternalPort() { } /** Any or all of recv... can be overloaded to provide the port's * functionality */ @@ -93,14 +93,14 @@ class ExternalMaster : public MemObject public: /** Create or find an external port which can be bound. Returns * NULL on failure */ - virtual Port *getExternalPort( + virtual ExternalPort *getExternalPort( const std::string &name, ExternalMaster &owner, const std::string &port_data) = 0; }; protected: /** The peer port for the gem5 port "port" */ - Port *externalPort; + ExternalPort *externalPort; /** Name of the bound port. This will be name() + ".port" */ std::string portName; @@ -120,9 +120,9 @@ class ExternalMaster : public MemObject public: ExternalMaster(ExternalMasterParams *params); - /** MasterPort interface. Responds only to port "port" */ - BaseMasterPort &getMasterPort(const std::string &if_name, - PortID idx = InvalidPortID); + /** Port interface. Responds only to port "port" */ + Port &getPort(const std::string &if_name, + PortID idx=InvalidPortID) override; /** Register a handler which can provide ports with port_type == * handler_name */ diff --git a/src/mem/external_slave.cc b/src/mem/external_slave.cc index ac93e669c..6266f6649 100644 --- a/src/mem/external_slave.cc +++ b/src/mem/external_slave.cc @@ -49,7 +49,7 @@ * a message. The stub port can be used to configure and test a system * where the external port is used for a peripheral before connecting * the external port */ -class StubSlavePort : public ExternalSlave::Port +class StubSlavePort : public ExternalSlave::ExternalPort { public: void processResponseEvent(); @@ -66,7 +66,7 @@ class StubSlavePort : public ExternalSlave::Port StubSlavePort(const std::string &name_, ExternalSlave &owner_) : - ExternalSlave::Port(name_, owner_), + ExternalSlave::ExternalPort(name_, owner_), responseEvent([this]{ processResponseEvent(); }, name()), responsePacket(NULL), mustRetry(false) { } @@ -83,7 +83,7 @@ class StubSlavePortHandler : public ExternalSlave::Handler { public: - ExternalSlave::Port *getExternalPort( + ExternalSlave::ExternalPort *getExternalPort( const std::string &name_, ExternalSlave &owner, const std::string &port_data) @@ -175,7 +175,7 @@ std::map ExternalSlave::portHandlers; AddrRangeList -ExternalSlave::Port::getAddrRanges() const +ExternalSlave::ExternalPort::getAddrRanges() const { return owner.addrRanges; } @@ -193,9 +193,8 @@ ExternalSlave::ExternalSlave(ExternalSlaveParams *params) : registerHandler("stub", new StubSlavePortHandler); } -BaseSlavePort & -ExternalSlave::getSlavePort(const std::string &if_name, - PortID idx) +Port & +ExternalSlave::getPort(const std::string &if_name, PortID idx) { if (if_name == "port") { DPRINTF(ExternalPort, "Trying to bind external port: %s %s\n", @@ -217,7 +216,7 @@ ExternalSlave::getSlavePort(const std::string &if_name, } return *externalPort; } else { - return MemObject::getSlavePort(if_name, idx); + return MemObject::getPort(if_name, idx); } } diff --git a/src/mem/external_slave.hh b/src/mem/external_slave.hh index 2bb0be869..7290d6339 100644 --- a/src/mem/external_slave.hh +++ b/src/mem/external_slave.hh @@ -67,18 +67,18 @@ class ExternalSlave : public MemObject { public: /** Derive from this class to create an external port interface */ - class Port : public SlavePort + class ExternalPort : public SlavePort { protected: ExternalSlave &owner; public: - Port(const std::string &name_, + ExternalPort(const std::string &name_, ExternalSlave &owner_) : SlavePort(name_, &owner_), owner(owner_) { } - ~Port() { } + ~ExternalPort() { } /** Any or all of recv... can be overloaded to provide the port's * functionality */ @@ -95,14 +95,14 @@ class ExternalSlave : public MemObject public: /** Create or find an external port which can be bound. Returns * NULL on failure */ - virtual Port *getExternalPort( + virtual ExternalPort *getExternalPort( const std::string &name, ExternalSlave &owner, const std::string &port_data) = 0; }; protected: /** The peer port for the gem5 port "port" */ - Port *externalPort; + ExternalPort *externalPort; /** Name of the bound port. This will be name() + ".port" */ std::string portName; @@ -126,9 +126,9 @@ class ExternalSlave : public MemObject public: ExternalSlave(ExternalSlaveParams *params); - /** SlavePort interface. Responds only to port "port" */ - BaseSlavePort &getSlavePort(const std::string &if_name, - PortID idx = InvalidPortID); + /** Port interface. Responds only to port "port" */ + Port &getPort(const std::string &if_name, + PortID idx=InvalidPortID) override; /** Register a handler which can provide ports with port_type == * handler_name */ diff --git a/src/mem/mem_checker_monitor.cc b/src/mem/mem_checker_monitor.cc index 75c797c32..8364b9198 100644 --- a/src/mem/mem_checker_monitor.cc +++ b/src/mem/mem_checker_monitor.cc @@ -73,23 +73,15 @@ MemCheckerMonitor::init() fatal("Communication monitor is not connected on both sides.\n"); } -BaseMasterPort& -MemCheckerMonitor::getMasterPort(const std::string& if_name, PortID idx) +Port & +MemCheckerMonitor::getPort(const std::string &if_name, PortID idx) { if (if_name == "master" || if_name == "mem_side") { return masterPort; - } else { - return MemObject::getMasterPort(if_name, idx); - } -} - -BaseSlavePort& -MemCheckerMonitor::getSlavePort(const std::string& if_name, PortID idx) -{ - if (if_name == "slave" || if_name == "cpu_side") { + } else if (if_name == "slave" || if_name == "cpu_side") { return slavePort; } else { - return MemObject::getSlavePort(if_name, idx); + return MemObject::getPort(if_name, idx); } } diff --git a/src/mem/mem_checker_monitor.hh b/src/mem/mem_checker_monitor.hh index e3a8832b5..0564a8178 100644 --- a/src/mem/mem_checker_monitor.hh +++ b/src/mem/mem_checker_monitor.hh @@ -70,11 +70,8 @@ class MemCheckerMonitor : public MemObject /** Destructor */ ~MemCheckerMonitor(); - virtual BaseMasterPort& getMasterPort(const std::string& if_name, - PortID idx = InvalidPortID); - - virtual BaseSlavePort& getSlavePort(const std::string& if_name, - PortID idx = InvalidPortID); + Port &getPort(const std::string &if_name, + PortID idx=InvalidPortID) override; virtual void init(); diff --git a/src/mem/mem_delay.cc b/src/mem/mem_delay.cc index b3c89d2a3..67a9664f8 100644 --- a/src/mem/mem_delay.cc +++ b/src/mem/mem_delay.cc @@ -60,23 +60,15 @@ MemDelay::init() } -BaseMasterPort& -MemDelay::getMasterPort(const std::string& if_name, PortID idx) +Port & +MemDelay::getPort(const std::string &if_name, PortID idx) { if (if_name == "master") { return masterPort; - } else { - return MemObject::getMasterPort(if_name, idx); - } -} - -BaseSlavePort& -MemDelay::getSlavePort(const std::string& if_name, PortID idx) -{ - if (if_name == "slave") { + } else if (if_name == "slave") { return slavePort; } else { - return MemObject::getSlavePort(if_name, idx); + return MemObject::getPort(if_name, idx); } } diff --git a/src/mem/mem_delay.hh b/src/mem/mem_delay.hh index 7ecb656f5..789d965c8 100644 --- a/src/mem/mem_delay.hh +++ b/src/mem/mem_delay.hh @@ -69,12 +69,9 @@ class MemDelay : public MemObject void init() override; - protected: // Port interfaces - BaseMasterPort& getMasterPort(const std::string &if_name, - PortID idx = InvalidPortID) override; - - BaseSlavePort& getSlavePort(const std::string &if_name, - PortID idx = InvalidPortID) override; + protected: // Port interface + Port &getPort(const std::string &if_name, + PortID idx=InvalidPortID) override; class MasterPort : public QueuedMasterPort { diff --git a/src/mem/mem_object.cc b/src/mem/mem_object.cc index 766eceeb7..c88905d09 100644 --- a/src/mem/mem_object.cc +++ b/src/mem/mem_object.cc @@ -47,15 +47,3 @@ MemObject::MemObject(const Params *params) : ClockedObject(params) { } - -BaseMasterPort& -MemObject::getMasterPort(const std::string& if_name, PortID idx) -{ - fatal("%s does not have any master port named %s\n", name(), if_name); -} - -BaseSlavePort& -MemObject::getSlavePort(const std::string& if_name, PortID idx) -{ - fatal("%s does not have any slave port named %s\n", name(), if_name); -} diff --git a/src/mem/mem_object.hh b/src/mem/mem_object.hh index e12b30661..3ae9c4adf 100644 --- a/src/mem/mem_object.hh +++ b/src/mem/mem_object.hh @@ -54,8 +54,7 @@ #include "sim/clocked_object.hh" /** - * The MemObject class extends the ClockedObject with accessor functions - * to get its master and slave ports. + * The MemObject class extends the ClockedObject for historical reasons. */ class MemObject : public ClockedObject { @@ -65,32 +64,6 @@ class MemObject : public ClockedObject { return dynamic_cast(_params); } MemObject(const Params *params); - - /** - * Get a master port with a given name and index. This is used at - * binding time and returns a reference to a protocol-agnostic - * base master port. - * - * @param if_name Port name - * @param idx Index in the case of a VectorPort - * - * @return A reference to the given port - */ - virtual BaseMasterPort& getMasterPort(const std::string& if_name, - PortID idx = InvalidPortID); - - /** - * Get a slave port with a given name and index. This is used at - * binding time and returns a reference to a protocol-agnostic - * base master port. - * - * @param if_name Port name - * @param idx Index in the case of a VectorPort - * - * @return A reference to the given port - */ - virtual BaseSlavePort& getSlavePort(const std::string& if_name, - PortID idx = InvalidPortID); }; #endif //__MEM_MEM_OBJECT_HH__ diff --git a/src/mem/qos/mem_sink.cc b/src/mem/qos/mem_sink.cc index 77cfbaf22..3ff2339d5 100644 --- a/src/mem/qos/mem_sink.cc +++ b/src/mem/qos/mem_sink.cc @@ -106,11 +106,11 @@ MemSinkCtrl::recvFunctional(PacketPtr pkt) pkt->popLabel(); } -BaseSlavePort & -MemSinkCtrl::getSlavePort(const std::string &interface, PortID idx) +Port & +MemSinkCtrl::getPort(const std::string &interface, PortID idx) { if (interface != "port") { - return MemObject::getSlavePort(interface, idx); + return MemObject::getPort(interface, idx); } else { return port; } diff --git a/src/mem/qos/mem_sink.hh b/src/mem/qos/mem_sink.hh index 84258e0ac..9a51269dc 100644 --- a/src/mem/qos/mem_sink.hh +++ b/src/mem/qos/mem_sink.hh @@ -133,12 +133,11 @@ class MemSinkCtrl : public MemCtrl /** * Getter method to access this memory's slave port * - * @param interface interface name + * @param if_name interface name * @param idx port ID number * @return reference to this memory's slave port */ - BaseSlavePort& getSlavePort(const std::string&, - PortID = InvalidPortID) override; + Port &getPort(const std::string &if_name, PortID=InvalidPortID) override; /** * Initializes this object diff --git a/src/mem/ruby/network/MessageBuffer.hh b/src/mem/ruby/network/MessageBuffer.hh index 69a0fb33e..4e85ac413 100644 --- a/src/mem/ruby/network/MessageBuffer.hh +++ b/src/mem/ruby/network/MessageBuffer.hh @@ -43,10 +43,12 @@ #include "base/trace.hh" #include "debug/RubyQueue.hh" +#include "mem/packet.hh" +#include "mem/port.hh" #include "mem/ruby/common/Address.hh" #include "mem/ruby/common/Consumer.hh" +#include "mem/ruby/network/dummy_port.hh" #include "mem/ruby/slicc_interface/Message.hh" -#include "mem/packet.hh" #include "params/MessageBuffer.hh" #include "sim/sim_object.hh" @@ -120,6 +122,12 @@ class MessageBuffer : public SimObject void setIncomingLink(int link_id) { m_input_link_id = link_id; } void setVnet(int net) { m_vnet_id = net; } + Port & + getPort(const std::string &, PortID idx=InvalidPortID) override + { + return RubyDummyPort::instance(); + } + void regStats(); // Function for figuring out if any of the messages in the buffer need diff --git a/src/mem/ruby/network/Network.hh b/src/mem/ruby/network/Network.hh index 7f5ed2aae..4e9791824 100644 --- a/src/mem/ruby/network/Network.hh +++ b/src/mem/ruby/network/Network.hh @@ -60,11 +60,13 @@ #include "base/addr_range.hh" #include "base/types.hh" #include "mem/packet.hh" +#include "mem/port.hh" #include "mem/protocol/LinkDirection.hh" #include "mem/protocol/MessageSizeType.hh" #include "mem/ruby/common/MachineID.hh" #include "mem/ruby/common/TypeDefines.hh" #include "mem/ruby/network/Topology.hh" +#include "mem/ruby/network/dummy_port.hh" #include "params/RubyNetwork.hh" #include "sim/clocked_object.hh" @@ -132,6 +134,12 @@ class Network : public ClockedObject */ NodeID addressToNodeID(Addr addr, MachineType mtype); + Port & + getPort(const std::string &, PortID idx=InvalidPortID) override + { + return RubyDummyPort::instance(); + } + protected: // Private copy constructor and assignment operator Network(const Network& obj); diff --git a/src/mem/ruby/network/dummy_port.hh b/src/mem/ruby/network/dummy_port.hh new file mode 100644 index 000000000..ca1ef4155 --- /dev/null +++ b/src/mem/ruby/network/dummy_port.hh @@ -0,0 +1,59 @@ +/* + * Copyright 2019 Google, Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Gabe Black + */ + +#ifndef __MEM_RUBY_NETWORK_DUMMY_PORT_HH__ +#define __MEM_RUBY_NETWORK_DUMMY_PORT_HH__ + +#include "mem/port.hh" + +class RubyDummyPort : public Port +{ + public: + RubyDummyPort() : Port("DummyPort", -1) {} + + void + bind(Port &peer) override + { + // No need to connect anything here currently. MessageBuffer + // port connections only serve to print the connections in + // the config output. + // TODO: Add real ports to MessageBuffers and use MemObject connect + // code below to bind MessageBuffer senders and receivers + } + void unbind() override {} + + static RubyDummyPort & + instance() + { + static RubyDummyPort dummy; + return dummy; + } +}; + +#endif //__MEM_RUBY_NETWORK_DUMMY_PORT_HH__ diff --git a/src/mem/ruby/slicc_interface/AbstractController.cc b/src/mem/ruby/slicc_interface/AbstractController.cc index 1327eccfb..fa1c936b7 100644 --- a/src/mem/ruby/slicc_interface/AbstractController.cc +++ b/src/mem/ruby/slicc_interface/AbstractController.cc @@ -229,9 +229,8 @@ AbstractController::isBlocked(Addr addr) return (m_block_map.count(addr) > 0); } -BaseMasterPort & -AbstractController::getMasterPort(const std::string &if_name, - PortID idx) +Port & +AbstractController::getPort(const std::string &if_name, PortID idx) { return memoryPort; } diff --git a/src/mem/ruby/slicc_interface/AbstractController.hh b/src/mem/ruby/slicc_interface/AbstractController.hh index 35cd3d2a5..5e39a28d2 100644 --- a/src/mem/ruby/slicc_interface/AbstractController.hh +++ b/src/mem/ruby/slicc_interface/AbstractController.hh @@ -126,8 +126,8 @@ class AbstractController : public MemObject, public Consumer virtual void initNetQueues() = 0; /** A function used to return the port associated with this bus object. */ - BaseMasterPort& getMasterPort(const std::string& if_name, - PortID idx = InvalidPortID); + Port &getPort(const std::string &if_name, + PortID idx=InvalidPortID); void queueMemoryRead(const MachineID &id, Addr addr, Cycles latency); void queueMemoryWrite(const MachineID &id, Addr addr, Cycles latency, diff --git a/src/mem/ruby/system/RubyPort.cc b/src/mem/ruby/system/RubyPort.cc index 84a70c0f1..795b473c7 100644 --- a/src/mem/ruby/system/RubyPort.cc +++ b/src/mem/ruby/system/RubyPort.cc @@ -87,53 +87,37 @@ RubyPort::init() m_mandatory_q_ptr = m_controller->getMandatoryQueue(); } -BaseMasterPort & -RubyPort::getMasterPort(const std::string &if_name, PortID idx) +Port & +RubyPort::getPort(const std::string &if_name, PortID idx) { if (if_name == "mem_master_port") { return memMasterPort; - } - - if (if_name == "pio_master_port") { + } else if (if_name == "pio_master_port") { return pioMasterPort; - } - - // used by the x86 CPUs to connect the interrupt PIO and interrupt slave - // port - if (if_name != "master") { - // pass it along to our super class - return MemObject::getMasterPort(if_name, idx); - } else { + } else if (if_name == "mem_slave_port") { + return memSlavePort; + } else if (if_name == "pio_slave_port") { + return pioSlavePort; + } else if (if_name == "master") { + // used by the x86 CPUs to connect the interrupt PIO and interrupt + // slave port if (idx >= static_cast(master_ports.size())) { - panic("RubyPort::getMasterPort: unknown index %d\n", idx); + panic("RubyPort::getPort master: unknown index %d\n", idx); } return *master_ports[idx]; - } -} - -BaseSlavePort & -RubyPort::getSlavePort(const std::string &if_name, PortID idx) -{ - if (if_name == "mem_slave_port") { - return memSlavePort; - } - - if (if_name == "pio_slave_port") - return pioSlavePort; - - // used by the CPUs to connect the caches to the interconnect, and - // for the x86 case also the interrupt master - if (if_name != "slave") { - // pass it along to our super class - return MemObject::getSlavePort(if_name, idx); - } else { + } else if (if_name == "slave") { + // used by the CPUs to connect the caches to the interconnect, and + // for the x86 case also the interrupt master if (idx >= static_cast(slave_ports.size())) { - panic("RubyPort::getSlavePort: unknown index %d\n", idx); + panic("RubyPort::getPort slave: unknown index %d\n", idx); } return *slave_ports[idx]; } + + // pass it along to our super class + return MemObject::getPort(if_name, idx); } RubyPort::PioMasterPort::PioMasterPort(const std::string &_name, diff --git a/src/mem/ruby/system/RubyPort.hh b/src/mem/ruby/system/RubyPort.hh index 146443282..922b3a973 100644 --- a/src/mem/ruby/system/RubyPort.hh +++ b/src/mem/ruby/system/RubyPort.hh @@ -148,10 +148,8 @@ class RubyPort : public MemObject void init() override; - BaseMasterPort &getMasterPort(const std::string &if_name, - PortID idx = InvalidPortID) override; - BaseSlavePort &getSlavePort(const std::string &if_name, - PortID idx = InvalidPortID) override; + Port &getPort(const std::string &if_name, + PortID idx=InvalidPortID) override; virtual RequestStatus makeRequest(PacketPtr pkt) = 0; virtual int outstandingCount() const = 0; diff --git a/src/mem/serial_link.cc b/src/mem/serial_link.cc index e1f3a001a..438fb0e68 100644 --- a/src/mem/serial_link.cc +++ b/src/mem/serial_link.cc @@ -93,24 +93,16 @@ SerialLink::SerialLink(SerialLinkParams *p) { } -BaseMasterPort& -SerialLink::getMasterPort(const std::string &if_name, PortID idx) +Port& +SerialLink::getPort(const std::string &if_name, PortID idx) { if (if_name == "master") return masterPort; - else - // pass it along to our super class - return MemObject::getMasterPort(if_name, idx); -} - -BaseSlavePort& -SerialLink::getSlavePort(const std::string &if_name, PortID idx) -{ - if (if_name == "slave") + else if (if_name == "slave") return slavePort; else // pass it along to our super class - return MemObject::getSlavePort(if_name, idx); + return MemObject::getPort(if_name, idx); } void diff --git a/src/mem/serial_link.hh b/src/mem/serial_link.hh index 6315f1b94..0bb1692ed 100644 --- a/src/mem/serial_link.hh +++ b/src/mem/serial_link.hh @@ -315,10 +315,8 @@ class SerialLink : public MemObject public: - virtual BaseMasterPort& getMasterPort(const std::string& if_name, - PortID idx = InvalidPortID); - virtual BaseSlavePort& getSlavePort(const std::string& if_name, - PortID idx = InvalidPortID); + Port &getPort(const std::string &if_name, + PortID idx=InvalidPortID); virtual void init(); diff --git a/src/mem/simple_mem.cc b/src/mem/simple_mem.cc index 64d7d204c..32fea1e89 100644 --- a/src/mem/simple_mem.cc +++ b/src/mem/simple_mem.cc @@ -231,11 +231,11 @@ SimpleMemory::recvRespRetry() dequeue(); } -BaseSlavePort & -SimpleMemory::getSlavePort(const std::string &if_name, PortID idx) +Port & +SimpleMemory::getPort(const std::string &if_name, PortID idx) { if (if_name != "port") { - return MemObject::getSlavePort(if_name, idx); + return MemObject::getPort(if_name, idx); } else { return port; } diff --git a/src/mem/simple_mem.hh b/src/mem/simple_mem.hh index 307981b80..c8c3db516 100644 --- a/src/mem/simple_mem.hh +++ b/src/mem/simple_mem.hh @@ -187,8 +187,8 @@ class SimpleMemory : public AbstractMemory DrainState drain() override; - BaseSlavePort& getSlavePort(const std::string& if_name, - PortID idx = InvalidPortID) override; + Port &getPort(const std::string &if_name, + PortID idx=InvalidPortID) override; void init() override; protected: diff --git a/src/mem/xbar.cc b/src/mem/xbar.cc index b139cdc9b..247024eff 100644 --- a/src/mem/xbar.cc +++ b/src/mem/xbar.cc @@ -81,27 +81,19 @@ BaseXBar::init() { } -BaseMasterPort & -BaseXBar::getMasterPort(const std::string &if_name, PortID idx) +Port & +BaseXBar::getPort(const std::string &if_name, PortID idx) { if (if_name == "master" && idx < masterPorts.size()) { // the master port index translates directly to the vector position return *masterPorts[idx]; } else if (if_name == "default") { return *masterPorts[defaultPortID]; - } else { - return MemObject::getMasterPort(if_name, idx); - } -} - -BaseSlavePort & -BaseXBar::getSlavePort(const std::string &if_name, PortID idx) -{ - if (if_name == "slave" && idx < slavePorts.size()) { + } else if (if_name == "slave" && idx < slavePorts.size()) { // the slave port index translates directly to the vector position return *slavePorts[idx]; } else { - return MemObject::getSlavePort(if_name, idx); + return MemObject::getPort(if_name, idx); } } diff --git a/src/mem/xbar.hh b/src/mem/xbar.hh index abe2a1096..0745ea5ac 100644 --- a/src/mem/xbar.hh +++ b/src/mem/xbar.hh @@ -413,10 +413,8 @@ class BaseXBar : public MemObject virtual void init(); /** A function used to return the port associated with this object. */ - BaseMasterPort& getMasterPort(const std::string& if_name, - PortID idx = InvalidPortID); - BaseSlavePort& getSlavePort(const std::string& if_name, - PortID idx = InvalidPortID); + Port &getPort(const std::string &if_name, + PortID idx=InvalidPortID) override; virtual void regStats(); diff --git a/src/python/SConscript b/src/python/SConscript index 36e0d5bfc..fb1666cd3 100644 --- a/src/python/SConscript +++ b/src/python/SConscript @@ -70,5 +70,4 @@ PySource('m5.ext.pyfdt', 'm5/ext/pyfdt/__init__.py') Source('pybind11/core.cc', add_tags='python') Source('pybind11/debug.cc', add_tags='python') Source('pybind11/event.cc', add_tags='python') -Source('pybind11/pyobject.cc', add_tags='python') Source('pybind11/stats.cc', add_tags='python') diff --git a/src/python/pybind11/pybind.hh b/src/python/pybind11/pybind.hh index 9a0643c5a..e2e470a18 100644 --- a/src/python/pybind11/pybind.hh +++ b/src/python/pybind11/pybind.hh @@ -46,7 +46,6 @@ void pybind_init_core(pybind11::module &m_native); void pybind_init_debug(pybind11::module &m_native); void pybind_init_event(pybind11::module &m_native); -void pybind_init_pyobject(pybind11::module &m_native); void pybind_init_stats(pybind11::module &m_native); #endif diff --git a/src/python/pybind11/pyobject.cc b/src/python/pybind11/pyobject.cc deleted file mode 100644 index bd363a132..000000000 --- a/src/python/pybind11/pyobject.cc +++ /dev/null @@ -1,126 +0,0 @@ -/* - * Copyright (c) 2017 ARM Limited - * All rights reserved - * - * The license below extends only to copyright in the software and shall - * not be construed as granting a license to any other intellectual - * property including but not limited to intellectual property relating - * to a hardware implementation of the functionality of the software - * licensed hereunder. You may use the software subject to the license - * terms below provided that you ensure that this notice is replicated - * unmodified and in its entirety in all distributions of the software, - * modified or unmodified, in source code or in binary form. - * - * Copyright (c) 2006 The Regents of The University of Michigan - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Nathan Binkert - */ - -#include "pybind11/pybind11.h" - -#include - -#include "config/the_isa.hh" - -#include "dev/net/etherdevice.hh" -#include "dev/net/etherint.hh" -#include "dev/net/etherobject.hh" -#include "mem/mem_object.hh" -#include "mem/ruby/network/Network.hh" -#include "mem/ruby/slicc_interface/AbstractController.hh" -#include "mem/ruby/system/Sequencer.hh" -#include "sim/full_system.hh" - -namespace py = pybind11; - -/** - * Connect the described MemObject ports. Called from Python. - * The indices i1 & i2 will be -1 for regular ports, >= 0 for vector ports. - * SimObject1 is the master, and SimObject2 is the slave - */ -static int -connectPorts(SimObject *o1, const std::string &name1, int i1, - SimObject *o2, const std::string &name2, int i2) -{ - auto *eo1 = dynamic_cast(o1); - auto *eo2 = dynamic_cast(o2); - - if (eo1 && eo2) { - EtherInt *p1 = eo1->getEthPort(name1, i1); - EtherInt *p2 = eo2->getEthPort(name2, i2); - - if (p1 && p2) { - p1->setPeer(p2); - p2->setPeer(p1); - - return 1; - } - } - - // These could be MessageBuffers from the ruby memory system. If so, they - // need not be connected to anything currently. - MessageBuffer *mb1, *mb2; - mb1 = dynamic_cast(o1); - mb2 = dynamic_cast(o2); - Network *nw1, *nw2; - nw1 = dynamic_cast(o1); - nw2 = dynamic_cast(o2); - - if ((mb1 || nw1) && (mb2 || nw2)) { - // No need to connect anything here currently. MessageBuffer - // connections in Python only serve to print the connections in - // the config output. - // TODO: Add real ports to MessageBuffers and use MemObject connect - // code below to bind MessageBuffer senders and receivers - return 1; - } - - MemObject *mo1, *mo2; - mo1 = dynamic_cast(o1); - mo2 = dynamic_cast(o2); - - if (mo1 == NULL || mo2 == NULL) { - panic ("Error casting SimObjects %s and %s to MemObject", o1->name(), - o2->name()); - } - - // generic master/slave port connection - BaseMasterPort& masterPort = mo1->getMasterPort(name1, i1); - BaseSlavePort& slavePort = mo2->getSlavePort(name2, i2); - - masterPort.bind(slavePort); - - return 1; -} - -void -pybind_init_pyobject(py::module &m_native) -{ - py::module m = m_native.def_submodule("pyobject"); - - m.def("connectPorts", &connectPorts); -} diff --git a/src/sim/SConscript b/src/sim/SConscript index a59b0ed1a..54e251287 100644 --- a/src/sim/SConscript +++ b/src/sim/SConscript @@ -55,6 +55,7 @@ Source('init.cc', add_tags='python') Source('init_signals.cc') Source('main.cc', tags='main') Source('port.cc') +Source('python.cc', add_tags='python') Source('root.cc') Source('serialize.cc') Source('drain.cc') diff --git a/src/sim/cxx_manager.cc b/src/sim/cxx_manager.cc index 915736127..35d008d58 100644 --- a/src/sim/cxx_manager.cc +++ b/src/sim/cxx_manager.cc @@ -471,9 +471,9 @@ CxxConfigManager::bindPort( * getCxxConfigDirectoryEntry for each object. */ /* It would be nice to be able to catch the errors from these calls. */ - BaseMasterPort &master_port = master_mem_object->getMasterPort( + Port &master_port = master_mem_object->getPort( master_port_name, master_port_index); - BaseSlavePort &slave_port = slave_mem_object->getSlavePort( + Port &slave_port = slave_mem_object->getPort( slave_port_name, slave_port_index); if (master_port.isConnected()) { diff --git a/src/sim/init.cc b/src/sim/init.cc index 5a49f360a..1fb7e6e1d 100644 --- a/src/sim/init.cc +++ b/src/sim/init.cc @@ -207,7 +207,6 @@ EmbeddedPyBind::initAll() pybind_init_debug(m_m5); pybind_init_event(m_m5); - pybind_init_pyobject(m_m5); pybind_init_stats(m_m5); for (auto &kv : getMap()) { diff --git a/src/sim/python.cc b/src/sim/python.cc new file mode 100644 index 000000000..159f32a8a --- /dev/null +++ b/src/sim/python.cc @@ -0,0 +1,48 @@ +/* + * Copyright 2019 Google, Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Gabe Black + */ + +#include "pybind11/pybind11.h" +#include "sim/init.hh" +#include "sim/port.hh" + +namespace +{ + +void +sim_pybind(pybind11::module &m_internal) +{ + pybind11::module m = m_internal.def_submodule("sim"); + pybind11::class_< + Port, std::unique_ptr>(m, "Port") + .def("bind", &Port::bind) + ; +} +EmbeddedPyBind embed_("sim", &sim_pybind); + +} // anonymous namespace diff --git a/src/sim/system.cc b/src/sim/system.cc index ffa8edaa6..2113fc079 100644 --- a/src/sim/system.cc +++ b/src/sim/system.cc @@ -218,8 +218,8 @@ System::init() panic("System port on %s is not connected.\n", name()); } -BaseMasterPort& -System::getMasterPort(const std::string &if_name, PortID idx) +Port & +System::getPort(const std::string &if_name, PortID idx) { // no need to distinguish at the moment (besides checking) return _systemPort; diff --git a/src/sim/system.hh b/src/sim/system.hh index 878c81252..69448d35f 100644 --- a/src/sim/system.hh +++ b/src/sim/system.hh @@ -128,8 +128,8 @@ class System : public MemObject /** * Additional function to return the Port of a memory object. */ - BaseMasterPort& getMasterPort(const std::string &if_name, - PortID idx = InvalidPortID) override; + Port &getPort(const std::string &if_name, + PortID idx=InvalidPortID) override; /** @{ */ /**