From: lkcl <lkcl@web>
Date: Fri, 12 Aug 2022 13:44:57 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~880
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d3dc8238eefeceaa9fa742252380d527acb6017c;p=libreriscv.git

---

diff --git a/openpower/sv/svp64_quirks.mdwn b/openpower/sv/svp64_quirks.mdwn
index e94681854..1ae1e7604 100644
--- a/openpower/sv/svp64_quirks.mdwn
+++ b/openpower/sv/svp64_quirks.mdwn
@@ -13,6 +13,8 @@ as a concept became popular.
    just because it is prefixed (semantic caveats below)
 3. A hardware-level for-loop (the prefix) makes vector elements
    100% synonymous with scalar instructions (the suffix)
+4. Exactly as with Scalar RISC ISAs, the uniformity does produce
+   "holes" in the encoding or some strange combinations.
 
 How can a Vector ISA even exist when no actual Vector instructions
 are permitted to be added? It comes down to the strict RISC abstraction.