From: whitequark Date: Wed, 3 Jun 2020 16:25:46 +0000 (+0000) Subject: flatten: simplify. NFC. X-Git-Tag: working-ls180~495^2~3 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d3e21003060a6395089a21ea2f81a7a689eb1884;p=yosys.git flatten: simplify. NFC. Remove redundant sigmaps. --- diff --git a/passes/techmap/flatten.cc b/passes/techmap/flatten.cc index 82e697495..75345fcc1 100644 --- a/passes/techmap/flatten.cc +++ b/passes/techmap/flatten.cc @@ -52,7 +52,6 @@ void apply_prefix(IdString prefix, RTLIL::SigSpec &sig, RTLIL::Module *module) struct FlattenWorker { dict>, RTLIL::Module*> cache; - dict sigmaps; pool flatten_do_list; pool flatten_done_list; @@ -122,6 +121,8 @@ struct FlattenWorker design->select(module, w); } + SigMap sigmap(module); + SigMap tpl_sigmap(tpl); pool tpl_written_bits; @@ -185,10 +186,7 @@ struct FlattenWorker // connect internal and external wires - if (sigmaps.count(module) == 0) - sigmaps[module].set(module); - - if (sigmaps.at(module)(c.first).has_const()) + if (sigmap(c.first).has_const()) log_error("Mismatch in directionality for cell port %s.%s.%s: %s <= %s\n", log_id(module), log_id(cell), log_id(it.first), log_signal(c.first), log_signal(c.second)); @@ -258,8 +256,6 @@ struct FlattenWorker bool did_something = false; LogMakeDebugHdl mkdebug; - SigMap sigmap(module); - for (auto cell : module->selected_cells()) { if (!design->has(cell->type))