From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Thu, 14 Feb 2019 09:41:13 +0000 (+0100)
Subject: soc/cores/clock: add actual clk_freqs to config
X-Git-Tag: 24jan2021_ls180~1393
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d3ecdd99959c730202bd2cf77880112059523d32;p=litex.git

soc/cores/clock: add actual clk_freqs to config
---

diff --git a/litex/soc/cores/clock.py b/litex/soc/cores/clock.py
index 8e2a24ba..785d971c 100644
--- a/litex/soc/cores/clock.py
+++ b/litex/soc/cores/clock.py
@@ -73,6 +73,7 @@ class S7Clocking(Module, AutoCSR):
                     for d in range(*self.clkout_divide_range):
                         clk_freq = vco_freq/d
                         if abs(clk_freq - f) < f*m:
+                            config["clkout{}_freq".format(n)] = clk_freq
                             config["clkout{}_divide".format(n)] = d
                             config["clkout{}_phase".format(n)] = p
                             valid = True
@@ -264,6 +265,7 @@ class USClocking(Module, AutoCSR):
                     for d in range(*self.clkout_divide_range):
                         clk_freq = vco_freq/d
                         if abs(clk_freq - f) < f*m:
+                            config["clkout{}_freq".format(n)] = clk_freq
                             config["clkout{}_divide".format(n)] = d
                             config["clkout{}_phase".format(n)] = p
                             valid = True
@@ -459,6 +461,7 @@ class ECP5PLL(Module):
                     for d in range(*self.clko_div_range):
                         clk_freq = vco_freq/d
                         if abs(clk_freq - f) < f*m:
+                            config["clko{}_freq".format(n)] = clk_freq
                             config["clko{}_div".format(n)] = d
                             config["clko{}_phase".format(n)] = p
                             valid = True