From: lkcl <lkcl@web>
Date: Wed, 19 Apr 2023 17:13:24 +0000 (+0100)
Subject: (no commit message)
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d3ecf33fa8566ef5436726f675bd8d9101243122;p=libreriscv.git

---

diff --git a/openpower/sv/rfc/ls013.mdwn b/openpower/sv/rfc/ls013.mdwn
index 39a0d81fe..45ead09f0 100644
--- a/openpower/sv/rfc/ls013.mdwn
+++ b/openpower/sv/rfc/ls013.mdwn
@@ -66,7 +66,8 @@ TODO
    Simple-V min/max Parallel Reduction is severely compromised.
 2. Once one FP min/max mode is implemented the rest are not much more
    hardware.
-3.  There exists similar instructions in VSX. This is frequently used to justify not
+3.  There exists similar instructions in VSX (not IEEE754-2019 though).
+   This is frequently used to justify not
    adding them. However SVP64/VSX may have different meaning from SVP64/SFFS,
     so it is *really* crucial to have SFFS ops even if "equivalent" to VSX
    in order for SVP64 to not be compromised (non-orthogonal).