From: Jim Wilson <jimw@sifive.com>
Date: Sat, 27 Jan 2018 00:00:11 +0000 (+0000)
Subject: RISC-V: Allow register pairs for 64-bit target.
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d3f952c5e03e5eb0382e8b24fe8339728a66b922;p=gcc.git

RISC-V: Allow register pairs for 64-bit target.

	gcc/
	* config/riscv/riscv.h (MAX_FIXED_MODE_SIZE): New.

From-SVN: r257114
---

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index d6af4524733..bcf3ffd079f 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,5 +1,7 @@
 2018-01-26  Jim Wilson  <jimw@sifive.com>
 
+	* config/riscv/riscv.h (MAX_FIXED_MODE_SIZE): New.
+
 	* config/riscv/elf.h (LIB_SPEC): Don't include -lgloss when nosys.specs
 	specified.
 
diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h
index a002bff4480..1c1c3431119 100644
--- a/gcc/config/riscv/riscv.h
+++ b/gcc/config/riscv/riscv.h
@@ -158,6 +158,10 @@ along with GCC; see the file COPYING3.  If not see
 
 #define PCC_BITFIELD_TYPE_MATTERS 1
 
+/* An integer expression for the size in bits of the largest integer machine
+   mode that should actually be used.  We allow pairs of registers.  */
+#define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TARGET_64BIT ? TImode : DImode)
+
 /* If defined, a C expression to compute the alignment for a static
    variable.  TYPE is the data type, and ALIGN is the alignment that
    the object would ordinarily have.  The value of this macro is used