From: Samuel Pitoiset Date: Thu, 31 Oct 2019 09:06:43 +0000 (+0100) Subject: radv: determine shaders wavesize at pipeline level X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d3f9957de4f2e1ba5a935caedbcc52222ab2087f;p=mesa.git radv: determine shaders wavesize at pipeline level Signed-off-by: Samuel Pitoiset Reviewed-by: Bas Nieuwenhuizen --- diff --git a/src/amd/compiler/aco_instruction_selection.cpp b/src/amd/compiler/aco_instruction_selection.cpp index 33242b7f6b7..85057d35bf5 100644 --- a/src/amd/compiler/aco_instruction_selection.cpp +++ b/src/amd/compiler/aco_instruction_selection.cpp @@ -153,7 +153,7 @@ static Temp emit_bpermute(isel_context *ctx, Builder &bld, Temp index, Temp data /* Currently not implemented on GFX6-7 */ assert(ctx->options->chip_class >= GFX8); - if (ctx->options->chip_class <= GFX9 || ctx->options->wave_size == 32) { + if (ctx->options->chip_class <= GFX9 || ctx->program->wave_size == 32) { return bld.ds(aco_opcode::ds_bpermute_b32, bld.def(v1), index_x4, data); } @@ -4927,7 +4927,7 @@ Temp get_scratch_resource(isel_context *ctx) scratch_addr = bld.smem(aco_opcode::s_load_dwordx2, bld.def(s2), scratch_addr, Operand(0u)); uint32_t rsrc_conf = S_008F0C_ADD_TID_ENABLE(1) | - S_008F0C_INDEX_STRIDE(ctx->options->wave_size == 64 ? 3 : 2);; + S_008F0C_INDEX_STRIDE(ctx->program->wave_size == 64 ? 3 : 2);; if (ctx->program->chip_class >= GFX10) { rsrc_conf |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) | diff --git a/src/amd/compiler/aco_instruction_selection_setup.cpp b/src/amd/compiler/aco_instruction_selection_setup.cpp index 3ab8ebb19eb..87868e43089 100644 --- a/src/amd/compiler/aco_instruction_selection_setup.cpp +++ b/src/amd/compiler/aco_instruction_selection_setup.cpp @@ -1250,7 +1250,7 @@ setup_isel_context(Program* program, program->info = info; program->chip_class = options->chip_class; program->family = options->family; - program->wave_size = options->wave_size; + program->wave_size = info->wave_size; program->lds_alloc_granule = options->chip_class >= GFX7 ? 512 : 256; program->lds_limit = options->chip_class >= GFX7 ? 65536 : 32768; @@ -1396,9 +1396,8 @@ setup_isel_context(Program* program, for (unsigned i = 0; i < shader_count; i++) scratch_size = std::max(scratch_size, shaders[i]->scratch_size); ctx.scratch_enabled = scratch_size > 0; - ctx.program->config->scratch_bytes_per_wave = align(scratch_size * ctx.options->wave_size, 1024); + ctx.program->config->scratch_bytes_per_wave = align(scratch_size * ctx.program->wave_size, 1024); ctx.program->config->float_mode = V_00B028_FP_64_DENORMS; - ctx.program->info->wave_size = ctx.options->wave_size; ctx.block = ctx.program->create_and_insert_block(); ctx.block->loop_nest_depth = 0; diff --git a/src/amd/vulkan/radv_nir_to_llvm.c b/src/amd/vulkan/radv_nir_to_llvm.c index 5b4ccc60e72..07c9d0e2a19 100644 --- a/src/amd/vulkan/radv_nir_to_llvm.c +++ b/src/amd/vulkan/radv_nir_to_llvm.c @@ -4778,7 +4778,7 @@ LLVMModuleRef ac_translate_nir_to_llvm(struct ac_llvm_compiler *ac_llvm, } ac_llvm_context_init(&ctx.ac, ac_llvm, options->chip_class, - options->family, float_mode, options->wave_size, 64); + options->family, float_mode, shader_info->wave_size, 64); ctx.context = ctx.ac.context; for (i = 0; i < MAX_SETS; i++) @@ -5125,7 +5125,6 @@ radv_compile_nir_shader(struct ac_llvm_compiler *ac_llvm, shader_info->gs.es_type = nir[0]->info.stage; } } - shader_info->wave_size = options->wave_size; } static void diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c index 8932d9fa54d..b239f024cbe 100644 --- a/src/amd/vulkan/radv_pipeline.c +++ b/src/amd/vulkan/radv_pipeline.c @@ -2378,6 +2378,21 @@ radv_fill_shader_keys(struct radv_device *device, keys[MESA_SHADER_FRAGMENT].fs.num_samples = key->num_samples; } +static uint8_t +radv_get_wave_size(struct radv_device *device, + gl_shader_stage stage, + const struct radv_shader_variant_key *key) +{ + if (stage == MESA_SHADER_GEOMETRY && !key->vs_common_out.as_ngg) + return 64; + else if (stage == MESA_SHADER_COMPUTE) + return device->physical_device->cs_wave_size; + else if (stage == MESA_SHADER_FRAGMENT) + return device->physical_device->ps_wave_size; + else + return device->physical_device->ge_wave_size; +} + static void radv_fill_shader_info(struct radv_pipeline *pipeline, struct radv_shader_variant_key *keys, @@ -2477,6 +2492,12 @@ radv_fill_shader_info(struct radv_pipeline *pipeline, radv_nir_shader_info_pass(nir[i], pipeline->layout, &keys[i], &infos[i]); } + + for (int i = 0; i < MESA_SHADER_STAGES; i++) { + if (nir[i]) + infos[i].wave_size = + radv_get_wave_size(pipeline->device, i, &keys[i]); + } } static void @@ -2807,6 +2828,7 @@ void radv_create_shaders(struct radv_pipeline *pipeline, radv_nir_shader_info_pass(nir[MESA_SHADER_GEOMETRY], pipeline->layout, &key, &info); + info.wave_size = 64; /* Wave32 not supported. */ pipeline->gs_copy_shader = radv_create_gs_copy_shader( device, nir[MESA_SHADER_GEOMETRY], &info, diff --git a/src/amd/vulkan/radv_shader.c b/src/amd/vulkan/radv_shader.c index c841a2f0726..4b48fd3dd46 100644 --- a/src/amd/vulkan/radv_shader.c +++ b/src/amd/vulkan/radv_shader.c @@ -1080,16 +1080,6 @@ shader_variant_compile(struct radv_device *device, options->has_ls_vgpr_init_bug = device->physical_device->rad_info.has_ls_vgpr_init_bug; options->use_ngg_streamout = device->physical_device->use_ngg_streamout; - if ((stage == MESA_SHADER_GEOMETRY && !options->key.vs_common_out.as_ngg) || - gs_copy_shader) - options->wave_size = 64; - else if (stage == MESA_SHADER_COMPUTE) - options->wave_size = device->physical_device->cs_wave_size; - else if (stage == MESA_SHADER_FRAGMENT) - options->wave_size = device->physical_device->ps_wave_size; - else - options->wave_size = device->physical_device->ge_wave_size; - if (!use_aco || options->dump_shader || options->record_ir) ac_init_llvm_once(); @@ -1114,7 +1104,7 @@ shader_variant_compile(struct radv_device *device, radv_init_llvm_compiler(&ac_llvm, thread_compiler, chip_family, tm_options, - options->wave_size); + info->wave_size); if (gs_copy_shader) { assert(shader_count == 1); diff --git a/src/amd/vulkan/radv_shader.h b/src/amd/vulkan/radv_shader.h index 0eca6ef0e79..0ee28b9aa3b 100644 --- a/src/amd/vulkan/radv_shader.h +++ b/src/amd/vulkan/radv_shader.h @@ -134,7 +134,6 @@ struct radv_nir_compiler_options { enum chip_class chip_class; uint32_t tess_offchip_block_dw_size; uint32_t address32_hi; - uint8_t wave_size; }; enum radv_ud_index {