From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 19 Dec 2019 17:21:33 +0000 (-0500)
Subject: Merge pull request #1569 from YosysHQ/eddie/fix_1531
X-Git-Tag: working-ls180~914
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d406f2ffd776e4f69c86a96db8e69a9aa8a1dc1c;p=yosys.git

Merge pull request #1569 from YosysHQ/eddie/fix_1531

verilog: preserve size of $genval$-s in for loops
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d406f2ffd776e4f69c86a96db8e69a9aa8a1dc1c