From: whitequark Date: Sat, 29 Dec 2018 15:02:04 +0000 (+0000) Subject: back.pysim: warn if simulation is not run. X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d410f0dcfe976216f093535e294d1eab7c8af7a8;p=nmigen.git back.pysim: warn if simulation is not run. This would have prevented 3ea35b85. --- diff --git a/nmigen/back/pysim.py b/nmigen/back/pysim.py index 7a5639c..0bcb0b3 100644 --- a/nmigen/back/pysim.py +++ b/nmigen/back/pysim.py @@ -1,5 +1,6 @@ import math import inspect +import warnings from contextlib import contextmanager from bitarray import bitarray from vcd import VCDWriter @@ -365,6 +366,8 @@ class Simulator: self._gtkw_file = gtkw_file self._traces = traces + self._run_called = False + while not isinstance(self._fragment, Fragment): self._fragment = self._fragment.get_fragment(platform=None) @@ -755,10 +758,14 @@ class Simulator: return False def run(self): + self._run_called = True + while self.step(): pass def run_until(self, deadline, run_passive=False): + self._run_called = True + while self._timestamp < deadline: if not self.step(run_passive): return False @@ -766,6 +773,9 @@ class Simulator: return True def __exit__(self, *args): + if not self._run_called: + warnings.warn("Simulation created, but not run", UserWarning) + if self._vcd_writer: vcd_timestamp = (self._timestamp + self._delta) / self._epsilon self._vcd_writer.close(vcd_timestamp) diff --git a/nmigen/test/test_sim.py b/nmigen/test/test_sim.py index cdd83d7..5b77222 100644 --- a/nmigen/test/test_sim.py +++ b/nmigen/test/test_sim.py @@ -530,3 +530,9 @@ class SimulatorIntegrationTestCase(FHDLTestCase): self.assertEqual((yield self.rdport.data), 0x33) sim.add_clock(1e-6) sim.add_process(process) + + def test_wrong_not_run(self): + with self.assertWarns(UserWarning, + msg="Simulation created, but not run"): + with Simulator(Fragment()) as sim: + pass