From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 3 Jun 2020 13:30:00 +0000 (+0100)
Subject: turn RegFiles into module, add all regfiles to it
X-Git-Tag: div_pipeline~633
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d419b2c5dafd3b6acac3f249f58c7d07844a12ce;p=soc.git

turn RegFiles into module, add all regfiles to it
---

diff --git a/src/soc/regfile/regfiles.py b/src/soc/regfile/regfiles.py
index dc92f0c4..ee9a7ff8 100644
--- a/src/soc/regfile/regfiles.py
+++ b/src/soc/regfile/regfiles.py
@@ -19,6 +19,7 @@ Links:
 
 # TODO
 
+from nmigen import Elaboratable, Module
 from soc.regfile.regfile import RegFile, RegFileArray
 from soc.regfile.virtual_port import VirtualRegPort
 from soc.decoder.power_enums import SPR
@@ -127,12 +128,21 @@ class SPRRegs(RegFile):
         self.w_ports = [self.write_port("dest")]
         self.r_ports = [self.read_port("src")]
 
-
-class RegFiles:
+# class containing all regfiles: int, cr, xer, fast, spr
+class RegFiles(Elaboratable):
     def __init__(self):
-        self.int = IntRegs()
-        self.cr = CRRegs()
-        self.xer = XERRegs()
-        self.fasr = FastRegs()
-        self.spr = SPRRegs()
+        self.rf = {}
+        for (name, kls) in [('int', IntRegs),
+                            ('cr', CRRegs),
+                            ('xer', XERRegs),
+                            ('fasr', FastRegs),
+                            ('spr', SPRRegs),]:
+            rf = self.rf[name] = kls()
+            setattr(self, name, rf)
+
+    def elaborate(self, platform):
+        m = Module()
+        for (name, rf) in self.rf.items():
+            setattr(m.submodules, name, rf)
+        return m