From: Eddie Hung <eddie@fpgeh.com>
Date: Sat, 5 Oct 2019 00:27:05 +0000 (-0700)
Subject: Use read_args for read_verilog
X-Git-Tag: working-ls180~881^2^2~183
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d4212d128b5985cf09f5e7f14bc06e7323e644ac;p=yosys.git

Use read_args for read_verilog
---

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index 16b607aac..caeeb3266 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -283,10 +283,13 @@ struct SynthXilinxPass : public ScriptPass
 			ff_map_file = "+/xilinx/xc7_ff_map.v";
 
 		if (check_label("begin")) {
+			std::string read_args;
 			if (vpr)
-				run("read_verilog -lib -D_ABC -D_EXPLICIT_CARRY +/xilinx/cells_sim.v");
-			else
-				run("read_verilog -lib -D_ABC +/xilinx/cells_sim.v");
+				read_args += " -D_EXPLICIT_CARRY";
+			if (abc9)
+				read_args += " -D_ABC9";
+			read_args += " -lib +/xilinx/cells_sim.v";
+			run("read_verilog" + read_args);
 
 			if (help_mode)
 				run("read_verilog -lib +/xilinx/{family}_cells_xtra.v");